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Altera_Forum's avatar
Altera_Forum
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16 years ago

Query on Delay block in singen.mdl

Hi, all,

I am getting start with singen.mdl as described in DSP builder User Guide.

I suppose the Delay (z^{-1}) introduces simply 1 clock delay. However, in addition to the delay by 1, every other SinDelay sample is missing. It seems downsampling takes place, but nowhere can I find a downsampling factor. It works after I replace that one with a new delay from blockset. Is that a bug in the model?

Thanks.

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Continue with this singen.mdl, when adding a clock to the model, we need to specify the 'real-world clock period', does it related to the development kit/FPGA board? Thanks.