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Altera_Forum
Honored Contributor
Honored ContributorQuery on Delay block in singen.mdl
Hi, all, I am getting start with singen.mdl as described in DSP builder User Guide. I suppose the Delay (z^{-1}) introduces simply 1 clock delay. However, in addition to the delay by 1, ...
Altera_ForumHonored Contributor
Honored ContributorContinue with this singen.mdl, when adding a clock to the model, we need to specify the 'real-world clock period', does it related to the development kit/FPGA board? Thanks.
