Quartus 18.1 2-PORT RAM MegaWizard bug

Question

Quartus 18.1 Lite bug. Create a Cyclone V project, open the MegaWizard for RAM 2-PORT, select M10K, true dual-port, set q_a width to 20 bits, check "Create byte enable for port A". The possibilities are 10 and 5 bits (correct), but the byteena_a bus is sized to (19:0) and the validator rejects the IP core parametrization. If the q_a width is set to 18 or 16, the wizard behaves correctly and byteena_a is (1:0). Should be the same in the 20-bit case.

anandraj_s_intel · Answer

Hi,What is the width of a byte for byte enable?If the width of the data input port is 20, you can only define the size of a byte as 5. In this case, you get a 4-bit byte-enable port.I was not able to replicate the scenario, byte_en[3:0] which is 4 bit after selecting M10K, true dual-port, set q_a width to 20 bits Please check the image attached..RegardsAnand

pwyde · Answer

Hi Anand,this was my first post to this forum and I didn't know I can post images. So here is what I do, step by step:

pwyde · Answer

One missing image:

anandraj_s_intel · Answer

Hi piotr,I got the problem,while setting 2-port ram the option " what is the width of a byte for byte enable?" drop down box by default have 10 bits selected, if we click on next we get this error.So just select 5 bit and reselect the 10 bit will eliminate the error.We can see correct byteena_a width. Let me know if this has helped resolve the issue you are facing or if you need any further assistance.RegardsAnand

Forum Discussion

Quartus 18.1 2-PORT RAM MegaWizard bug

4 Replies

Recent Discussions

Constraints not being picked for DCFIFO

Cyclone 10 GX IBIS-AMI models

F-Tile Ethernet Hard IP (100G)

Cyclone® 10 GX Avalon®-ST Interface for PCI Express example Simulation

Agilex-7 AXI MCDMA for PCIe hang