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PWyde's avatar
PWyde
Icon for New Contributor rankNew Contributor
7 years ago

Quartus 18.1 2-PORT RAM MegaWizard bug

Quartus 18.1 Lite bug. Create a Cyclone V project, open the MegaWizard for RAM 2-PORT, select M10K, true dual-port, set q_a width to 20 bits, check "Create byte enable for port A". The possibilities are 10 and 5 bits (correct), but the byteena_a bus is sized to (19:0) and the validator rejects the IP core parametrization. If the q_a width is set to 18 or 16, the wizard behaves correctly and byteena_a is (1:0). Should be the same in the 20-bit case.

4 Replies

  • AnandRaj_S_Intel's avatar
    AnandRaj_S_Intel
    Icon for Regular Contributor rankRegular Contributor
    7 years ago

    Hi,

    1. What is the width of a byte for byte enable?

    If the width of the data input port is 20, you can only define the size of a byte as 5. In this case, you get a 4-bit byte-enable port.

    I was not able to replicate the scenario, byte_en[3:0] which is 4 bit after selecting M10K, true dual-port, set q_a width to 20 bits Please check the image attached..

    Regards

    Anand

    • PWyde's avatar
      PWyde
      Icon for New Contributor rankNew Contributor
      7 years ago

      Hi Anand,

      this was my first post to this forum and I didn't know I can post images. So here is what I do, step by step: