Forum Discussion

PWyde's avatar
PWyde
Icon for New Contributor rankNew Contributor
7 years ago

Quartus 18.1 2-PORT RAM MegaWizard bug

Quartus 18.1 Lite bug. Create a Cyclone V project, open the MegaWizard for RAM 2-PORT, select M10K, true dual-port, set q_a width to 20 bits, check "Create byte enable for port A". The possibilities ...
AnandRaj_S_Intel's avatar
AnandRaj_S_Intel
Icon for Regular Contributor rankRegular Contributor
7 years ago

Hi,

  1. What is the width of a byte for byte enable?

If the width of the data input port is 20, you can only define the size of a byte as 5. In this case, you get a 4-bit byte-enable port.

I was not able to replicate the scenario, byte_en[3:0] which is 4 bit after selecting M10K, true dual-port, set q_a width to 20 bits Please check the image attached..

Regards

Anand

PWyde's avatar
PWyde
Icon for New Contributor rankNew Contributor
7 years ago

Hi Anand,

this was my first post to this forum and I didn't know I can post images. So here is what I do, step by step:

  • PWyde's avatar
    PWyde
    Icon for New Contributor rankNew Contributor
    7 years ago

    One missing image:

  • AnandRaj_S_Intel's avatar
    AnandRaj_S_Intel
    Icon for Regular Contributor rankRegular Contributor
    7 years ago

    Hi piotr,

    I got the problem,

    while setting 2-port ram the option " what is the width of a byte for byte enable?" drop down box by default have 10 bits selected, if we click on next we get this error.

    So just select 5 bit and reselect the 10 bit will eliminate the error.

    We can see correct byteena_a width.

    Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

    Regards

    Anand