Qsys custom IP component for Maxim MAX1304/08/12 ADC

Greetings,

I am trying to integrate MAXIM MAX1304 ADC to NIOS in a Cyclone 3, it is working for the most part. I was wondering if I could get an expert review from gurus in this forum and see if we could increase the FIFO depth somehow.

My system uses Cyclone III EP3C10F256 FPGA and there is other stuff in it as well including a NIOS economy core. Originally I had FIFO depth 64 and NIOS onchip boot memory 32K. I realized that the bootloader is only taking 16K so I could reduce memory size it and there will be space left to increase the FIFO depth. Obviously I don't understand this because reducing onchip memory to 20K reduced total memory bits while increasing FIFO depth to 128 samples increased total logic element usage.

With onchip memory 20K and ADC FIFO depth 128 samples, I am at 92% LE & 44% RAM bits consumption.

Now my question to the gurus in here, is there a way to use available ram bits for FIFO instead of logic elements? I am asking this because if changing onchip memory size affects total ram bits, why can I not use the same ram bits to build my FIFO because in theory a FIFO is a 15 bit wide 128 sample deep piece of memory anyway, right?

Thanks in advance,

Hasan Rizvi