Honored Contributor
Honored ContributorHi Hasan:
I've looked at your code, and there's a few things I'm seeing: 1: Your Fifo logic is intermixed with your state machine logic. It's better to separate the memory into it's own module, so that you can control the synthesis a little better. 2: Your defininition of fifo_data_array, has a non- power of 2 size. 129 location (128:0) This may cause the synthesis engine to not reference a memory. 3: I was taught that memories should be defined as reg [14:0] data_fifo_array[0:127]. This makes a difference when you are pre-filling the memory with a $readmemh, so it may be causing the synthesis tool to not properly identify the memory as well. 4: (Optional). I tend to make the size of the fifo fit the memory block size for that bit width. Since you are using a Cylone 3 family, for 15 bits of data, the "Optimal" size would be 512 locations. Based on http://www.altera.com/literature/hb/cyc3/cyc3_ciii51004.pdf page 2 (512x16 or 512x18) Hope this helps. Pete www.infinetix.com
