Occasional Contributor
Regular ContributorHello,
To view the system interconnect, you can go to Platform Designer -> System -> Show System with Platform Designer Interconnect.
Then you can add the interconnect signal into SignalTap to see the data.
I think you can check if there is any warning in the Analysis & Synthesis compilation report related to address range of the memory transfer.
Try to solve the timing issue first, it can impact the memory functionality.
Check the DDR Report for the summary of the memory timing.
Also check for the path the timing is not meet. from which modules to which.
I expect this timing may occur in core timing path.
Regards,
Adzim
Occasional ContributorHello,
I found that the waitrequest every 2080 cycle is related with the refresh interval "tREFI" of 7,8 µs which exactly corresponds with 2080 cycles at 266 MHz. So I believe everything works well, I just have to take this into account for estimating maximum DDR datarate which is about 65Gbps instead of 68Gbps, which is fine.
For Timing errors, I don't have any setup error, but I have 4 hold errors for instance with this path :
-0.346 u0|emif_0|emif_0|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].tile_ctrl_inst|pa_core_clk_out[0] auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|auto_signaltap_auto_signaltap_0|sld_signaltap_inst|acq_data_in_reg[102] u0|emif_0|emif_0_core_usr_clk u0|emif_0|emif_0_core_usr_clk 0.000 3.609 3.688 Slow 900mV 0C Model
Also I have 1 single timing error in the "Report DDR" of the timing analyser, for all 4 models (slow/fast/0C/100C), which is on the "Read Capture" signal of EMIF :
Actually the design works but I don't know what to do with these errors, do you believe it is relevant to fix them ? Maybe this is only due to signaltap logic.
Thanks
Super ContributorYes, remove Signal Tap and see if you are still having timing issues.
