Problems with Deinterlacer IP

Hello,

I have some trouble about the use of Deinterlacer IP from Altera VIP suite. So I'm asking you some questions.

In my design, my FPGA doesn't have to do any kind of video elaboration, because we have a graphic processor which has to do that. This is the routing of video signal:

video PAL -> video decoder -> FPGA (only routing) -> processor (with some elaborations) -> FPGA (only routing) -> encoder -> LVDS

Unfortunately, the processor can't deinterlace the video, so that, when there is a movement, we experience lines on the moving objects.

So I decided to use the Deinterlacer IP from VIP suite. I thought that this routing could work:

video PAL (digital) -> Clocked Video Input IP (interlaced video) -> Deinterlacer -> Clocked Video Output IP (progressive video)

(Please see the picture)

https://www.alteraforum.com/forum/attachment.php?attachmentid=8581

As I am new with VIP suite, at first I used only CVI -> CVO, without any elaboration. All is fine with these settings: 720 x 576 the resolution, 8 bit per color plane, 2 color planes in sequence, sync embedded in video. These settings are both for CVI and CVO.

Then I put the deinterlacer setting a BOB scanline duplication algorithm without Frame Buffer. CVO is now not for interlaced video and has these parameters:

Active picture line: 45

Ancillary packet insertion: 8

Horizontal blanking: 144

Vertical blanking: 49

only for Frame/Field 1 in Embedded Sync Configuration. The other are all 0.

The result is that I see only few lines on top of the screen, but the other pixel aren't ok, there is no image. Please note that the first lines have been correctly deinterlaced.

I also checked control packets on Signal Tap II and after the deinterlacer IP I see a progressive code correctly.

Why have I this issue? Is that a troughput problem? Do I have to use necessarily a Frame Buffer? If yes, how can I do that without a ddr ram on my board?

Thank you for your attention