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Altera_Forum
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12 years ago

Problems with Deinterlacer IP

Hello, I have some trouble about the use of Deinterlacer IP from Altera VIP suite. So I'm asking you some questions. In my design, my FPGA doesn't have to do any kind of video elaboration, becau...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Hello,

I've found overflow and underflow (in CVI and CVO) going to 1 and stayng still 1 while looking in SignalTap. I'm quite sure the problem is about troughput. I've the FIFO for the CVI equal to 1920 and the one in the CVO 1440 with 1439 the level for starting output (I've doubled the 720 lines of the progressive PAL, because of the BOB duplication algorithm).

But nothing solved the problem, I still see few deinterlaced lines and after nonsense pixels.