Problems with DDR2 high performance controller 8.1

This is most likely because the fitter can't place the clock source for the PLL on an IO bank next to the PLL, because the IO standard of the clock_source pin is different to the rest of the IO bank.

Try changing clock_source to a 1.8v IO standard and see if that fixes things. Long term you'll want to look at the PLL clock routing and manually assign the DDR pins and the clock_source pin to different IO banks.

thanks cajun-rat for your fast reply!

I just checked the io standard assignment in the pin planer and it is set 1.8V. Where did you see that the io assignment isn't set to 1.8V?

I suspect there is a reason why Quartus isn't placing clock_source near the PLL. One way to find out why is to manually place the PLL on the same side of the chip as your memory interface, then manually place the clock_source pin on one of the dedicated input pins that feed it (the Clocking and PLLs section of the Stratix III datasheet has the diagrams you need).

With this in place you will force the issue, and the compile will most likely fail with a big long warning, but in the end there must be some reason why it can't place the clock input pin in a sensible place. I suspect IO bank voltages, but it might be something else.

Also: are the pnf_* signals and other non-memory interface signals placed out of the way? They might be what is stopping it working.