Problems with DDR2 high performance controller 8.1

This is most likely because the fitter can't place the clock source for the PLL on an IO bank next to the PLL, because the IO standard of the clock_source pin is different to the rest of the IO bank.

Try changing clock_source to a 1.8v IO standard and see if that fixes things. Long term you'll want to look at the PLL clock routing and manually assign the DDR pins and the clock_source pin to different IO banks.