Occasional ContributorProblems when using FIFO IP for simulation
I defined a IP based on original Intel FIFO IP, and used in platform designer.
sink_clk, //50MHz
source_clk, //75MHz
reset_n,
sink_avalonst_data,
sink_avalonst_valid,
sink_avalonst_ready,
source_avalonst_data,
source_avalonst_valid,
source_avalonst_ready,
fifo_ready
);
input sink_clk;
input source_clk;
input reset_n;
input [15:0] sink_avalonst_data;
input sink_avalonst_valid;
output sink_avalonst_ready;
output [63:0] source_avalonst_data;
output source_avalonst_valid;
input source_avalonst_ready;
output fifo_ready;
/********************************************************************************************************************************\
part 0: Internal parameter
\********************************************************************************************************************************/
wire [8:0] rdusedw;
/********************************************************************************************************************************\
part 1: FIFO
\********************************************************************************************************************************/
adcfifo fifo(
.data (sink_avalonst_data),
.wrclk (sink_clk),
.wrreq (sink_avalonst_valid),
.q (source_avalonst_data),
.rdclk (source_clk),
.rdreq (source_avalonst_ready),
.rdusedw (rdusedw),
.aclr (~reset_n)
);
assign source_avalonst_valid = rdusedw[8] & reset_n;
assign sink_avalonst_ready = (rdusedw < 9'd511);
assign fifo_ready = rdusedw[8] & reset_n;
It can not be successfully simulated in modelsim-intel. Based on IP, it requires altera_mf.
This is already in modelsim searched libraries. So I don't know why it still fails.
The error message is as below. adcfifo is qip I generated based on Intel FIFO IP.
adc_fifo.v(41): Instantiation of 'adcfifo' failed. The design unit was not found.
# Searched libraries:
# C:/intelFPGA/18.0/modelsim_ae/altera/verilog/altera
# C:/intelFPGA/18.0/modelsim_ae/altera/verilog/220model
# C:/intelFPGA/18.0/modelsim_ae/altera/verilog/sgate
# C:/intelFPGA/18.0/modelsim_ae/altera/verilog/altera_mf
# C:/intelFPGA/18.0/modelsim_ae/altera/verilog/altera_lnsim
# C:/intelFPGA/18.0/modelsim_ae/altera/verilog/fiftyfivenm
