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XQSHEN's avatar
XQSHEN
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Problems when using FIFO IP for simulation

I defined a IP based on original Intel FIFO IP, and used in platform designer. module adc_fifo( sink_clk, //50MHz source_clk, //75MHz reset_n, sink_avalonst_data, sink_avalonst_va...
XQSHEN's avatar
XQSHEN
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Yes, the adcfifo.v is in the qip files. Actually I already include qip in below two methods, but it still doesn't work.

1) add qip through assignment - > setting - > files

2) add qip in platform designer -> component editor -> files -> both synthese file and simulation files.

RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
5 years ago

Which Quartus version are you using? Standard or pro?

Could you share your project so I can investigate further? A simplified design that can duplicate the issue will do.

  • XQSHEN's avatar
    XQSHEN
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    Quartus prime 18.0, standard version.

    I just solved the issue by adding adcfifo.v in the component editor simulation files.

    1) Add adcfifo.v --> it works.

    2) Add adcfifo.qip --> it doesn't work.