problem with DDR2 SDRAM controller

Question

hello

i have a little problem with the DDR2 SDRAM high performance controler that i create using Mega Wizard application.

i have created it and it was successfully compiled in Quartus (8.1 if thats matters) and simulated by the Quartus program (with modelsim 6.3).

then i wrote a little wrapper entity to match the example design to my needs and it also successfully compiled and simulated by the Quartus.

but i noticed something weird : when i compile the files manually and simulate them (using standart vhdl 93 compiler and modelsim 6.3) i notice a weird warnings - some signals may have multiple drivers.

the problem is that the warning refer to a file that the Mega Wizard generated and i didnt touch it.

the problematic file is <my design name>_phy_alt_mem_phy_seq.vhd

the problematic signals are: mmi_ctrl, parameterisation_rec and mmi_pll.

by the way the simulation is running fine although the warnings...

my questions are:

1) are those warning important? the simulation is running fine.

2) how do i fix those warnings (even if they are not important they are still annoying and can mask more critical warnings)

thank you for reading and answering

altera_forum · Answer

Can you provide us with the explicit printout from ModelSim?  Jake

altera_forum · Answer

i dont really sure which printout you need so i hope you want those:   warnings when compiling the libraries:   
** Warning:  /&lt;path for altera&gt;/altera/quartus2/9.0/quartus/eda/sim_lib/stratixiv_atoms.vhd(1852): VITAL timing generic missing port reference(s).
(1076.4 section 4.3.2.1.2)
 i dont really why there is a warning here because i didnt touch that file...   ------------------------------------------------- warnings when compiling the files:   i'm using liunx this command in linux environment : vcom -O4 -work modelsim_work -93 -quiet -nologo -explicit -source &lt;mega wizard path&gt;/&lt;device name&gt;_phy_alt_mem_phy_seq.vhd   (all the other files necessary have been compiled without warnings)    the warnings for this file are:    # ##### /&lt;mega wizard path&gt;/&lt;device name&gt;_phy_alt_mem_phy_seq.vhd(12028):     signal mmi_ctrl                       : t_mmi_ctrl;
** Warning:  ../vhdl/vendors_ips/mega_wizard/&lt;device name&gt;/&lt;device name&gt;_phy_alt_mem_phy_seq.vhd(12028): Nonresolved signal 'mmi_ctrl' may have multiple sources.
  Drivers:
    /&lt;mega wizard path&gt;/&lt;device name&gt;_phy_alt_mem_phy_seq.vhd(12306):Statement mmi
    /&lt;mega wizard path&gt;/&lt;device name&gt;_phy_alt_mem_phy_seq.vhd(12455):Process line__12455
       Driven at:
          /&lt;mega wizard path&gt;/&lt;device name&gt;_phy_alt_mem_phy_seq.vhd(12462)
 # ##### /&lt;mega wizard path&gt;/&lt;device name&gt;_phy_alt_mem_phy_seq.vhd(12064):     signal parameterisation_rec           : t_algm_paramaterisation;
** Warning:  /&lt;mega wizard path&gt;/&lt;device name&gt;_phy_alt_mem_phy_seq.vhd(12064): Nonresolved signal 'parameterisation_rec' may have multiple sources.
  Drivers:
    /&lt;mega wizard path&gt;/&lt;device name&gt;_phy_alt_mem_phy_seq.vhd(12306):Statement mmi
    /&lt;mega wizard path&gt;/&lt;device name&gt;_phy_alt_mem_phy_seq.vhd(12455):Process line__12455
       Driven at:
          /&lt;mega wizard path&gt;/&lt;device name&gt;_phy_alt_mem_phy_seq.vhd(12460)# ##### /&lt;mega wizard path&gt;/&lt;device name&gt;_phy_alt_mem_phy_seq.vhd(12077):     signal mmi_pll                        : t_mmi_pll_reconfig;
** Warning:  /&lt;mega wizard path&gt;/&lt;device name&gt;_phy_alt_mem_phy_seq.vhd(12077): Nonresolved signal 'mmi_pll' may have multiple sources.
  Drivers:
    /&lt;mega wizard path&gt;/&lt;device name&gt;_phy_alt_mem_phy_seq.vhd(12306):Statement mmi
    /&lt;mega wizard path&gt;/&lt;device name&gt;_phy_alt_mem_phy_seq.vhd(12455):Process line__12455
       Driven at:
          /&lt;mega wizard path&gt;/&lt;device name&gt;_phy_alt_mem_phy_seq.vhd(12461)

altera_forum · Answer

here are printout from modelsim transcript:   those warnings is showen only when i run the simulation, there are no warnings when i load the simulation     
** Warning: Warning: Value for read_during_write_mode_mixed_ports is not honoured in DUAL_PORT operation mode when output registers are not clocked by clock0 for ram_block_type LUTRAM#  Time: 0 ps Iteration: 0 Instance: /&lt;device name&gt;_tb/ddr2_if_1/u_&lt;device name&gt;/&lt;device name&gt;_controller_phy_inst/&lt;device name&gt;_phy_inst/&lt;device name&gt;_phy_&lt;device name&gt;_phy_alt_mem_phy_&lt;device name&gt;_phy_alt_mem_phy_inst_&lt;device name&gt;_phy_alt_mem_phy_read_dp_group_fr_rdp_rdp_per_group_1_rdp_altsyncram_ram_6752#  ** Warning: Warning: Value for read_during_write_mode_mixed_ports is not honoured in DUAL_PORT operation mode when output registers are not clocked by clock0 for ram_block_type LUTRAM#  Time: 0 ps Iteration: 0 Instance: /&lt;device name&gt;_tb/ddr2_if_1/u_&lt;device name&gt;/&lt;device name&gt;_controller_phy_inst/&lt;device name&gt;_phy_inst/&lt;device name&gt;_phy_&lt;device name&gt;_phy_alt_mem_phy_&lt;device name&gt;_phy_alt_mem_phy_inst_&lt;device name&gt;_phy_alt_mem_phy_read_dp_group_fr_rdp_rdp_per_group_0_rdp_altsyncram_ram_6829#  ** Warning: Warning: Value for read_during_write_mode_mixed_ports is not honoured in DUAL_PORT operation mode when output registers are not clocked by clock0 for ram_block_type LUTRAM#  Time: 0 ps Iteration: 0 Instance: /&lt;device name&gt;_tb/ddr2_if_1/u_&lt;device name&gt;/&lt;device name&gt;_controller_phy_inst/&lt;device name&gt;_phy_inst/&lt;device name&gt;_phy_&lt;device name&gt;_phy_alt_mem_phy_&lt;device name&gt;_phy_alt_mem_phy_inst_&lt;device name&gt;_phy_alt_mem_phy_postamble_fr_poa_gen_poa_group_1_poa_altsyncram_altsyncram_component_6085#  ** Warning: Warning: Value for read_during_write_mode_mixed_ports is not honoured in DUAL_PORT operation mode when output registers are not clocked by clock0 for ram_block_type LUTRAM#  Time: 0 ps Iteration: 0 Instance: /&lt;device name&gt;_tb/ddr2_if_1/u_&lt;device name&gt;/&lt;device name&gt;_controller_phy_inst/&lt;device name&gt;_phy_inst/&lt;device name&gt;_phy_&lt;device name&gt;_phy_alt_mem_phy_&lt;device name&gt;_phy_alt_mem_phy_inst_&lt;device name&gt;_phy_alt_mem_phy_postamble_fr_poa_gen_poa_group_0_poa_altsyncram_altsyncram_component_6102#  ** Note: Stratix IV PLL was reset#  Time: 0 ps Iteration: 8 Instance: /&lt;device name&gt;_tb/ddr2_if_1/u_&lt;device name&gt;/&lt;device name&gt;_controller_phy_inst/&lt;device name&gt;_phy_inst/&lt;device name&gt;_phy_&lt;device name&gt;_phy_alt_mem_phy_&lt;device name&gt;_phy_alt_mem_phy_inst_&lt;device name&gt;_phy_alt_mem_phy_clk_reset_clk_&lt;device name&gt;_phy_alt_mem_phy_pll_full_rate1_pll_5977/altpll_component/stratixiii_altpll/m4#  ** Warning: Illegal value detected on input clock.#  Time: 100 ns Iteration: 13 Instance: /&lt;device name&gt;_tb/ddr2_if_1/u_&lt;device name&gt;/&lt;device name&gt;_controller_phy_inst/&lt;device name&gt;_phy_inst/&lt;device name&gt;_phy_&lt;device name&gt;_phy_alt_mem_phy_&lt;device name&gt;_phy_alt_mem_phy_inst_&lt;device name&gt;_phy_alt_mem_phy_clk_reset_clk_stratixiii_dll_dll_5708#  ** Note: Stratix IV PLL locked to incoming clock#  Time: 118784 ps Iteration: 0 Instance: /&lt;device name&gt;_tb/ddr2_if_1/u_&lt;device name&gt;/&lt;device name&gt;_controller_phy_inst/&lt;device name&gt;_phy_inst/&lt;device name&gt;_phy_&lt;device name&gt;_phy_alt_mem_phy_&lt;device name&gt;_phy_alt_mem_phy_inst_&lt;device name&gt;_phy_alt_mem_phy_clk_reset_clk_&lt;device name&gt;_phy_alt_mem_phy_pll_full_rate1_pll_5977/altpll_component/stratixiii_altpll/m4#  ** Note: #  Time: 131288 ps Iteration: 8 Instance: /&lt;device name&gt;_tb/ddr2_if_1/u_&lt;device name&gt;/&lt;device name&gt;_controller_phy_inst/&lt;device name&gt;_phy_inst/&lt;device name&gt;_phy_&lt;device name&gt;_phy_alt_mem_phy_&lt;device name&gt;_phy_alt_mem_phy_inst_&lt;device name&gt;_phy_alt_mem_phy_seq_wrapper_seq_wrapper_6153/&lt;device name&gt;_phy_alt_mem_phy_seq_wrapper_&lt;device name&gt;_phy_alt_mem_phy_seq_seq_inst_1453/reporting#  ** Note: DLL to lock to incoming clock#  Time: 2786304 ps Iteration: 9 Instance: /&lt;device name&gt;_tb/ddr2_if_1/u_&lt;device name&gt;/&lt;device name&gt;_controller_phy_inst/&lt;device name&gt;_phy_inst/&lt;device name&gt;_phy_&lt;device name&gt;_phy_alt_mem_phy_&lt;device name&gt;_phy_alt_mem_phy_inst_&lt;device name&gt;_phy_alt_mem_phy_clk_reset_clk_stratixiii_dll_dll_5708#  ** Note: &lt;device name&gt;_phy_alt_mem_phy_seq (dgrb) : gathered resync phase samples (for mtp alignment 0) is DGRB_PHASE_SAMPLES: 00000000111111111111111111111111111111111111111100000000000000000000000000000000#  Time: 109778864 ps Iteration: 8 Instance: /&lt;device name&gt;_tb/ddr2_if_1/u_&lt;device name&gt;/&lt;device name&gt;_controller_phy_inst/&lt;device name&gt;_phy_inst/&lt;device name&gt;_phy_&lt;device name&gt;_phy_alt_mem_phy_&lt;device name&gt;_phy_alt_mem_phy_inst_&lt;device name&gt;_phy_alt_mem_phy_seq_wrapper_seq_wrapper_6153/&lt;device name&gt;_phy_alt_mem_phy_seq_wrapper_&lt;device name&gt;_phy_alt_mem_phy_seq_seq_inst_1453/dgrb/rsc_block#  ** Note: &lt;device name&gt;_phy_alt_mem_phy_seq (dgrb) : gathered resync phase samples (for mtp alignment 1) is DGRB_PHASE_SAMPLES: 00000000000000000000000000000000000000000000000000000000000000000000000000000000#  Time: 208693840 ps Iteration: 8 Instance: /&lt;device name&gt;_tb/ddr2_if_1/u_&lt;device name&gt;/&lt;device name&gt;_controller_phy_inst/&lt;device name&gt;_phy_inst/&lt;device name&gt;_phy_&lt;device name&gt;_phy_alt_mem_phy_&lt;device name&gt;_phy_alt_mem_phy_inst_&lt;device name&gt;_phy_alt_mem_phy_seq_wrapper_seq_wrapper_6153/&lt;device name&gt;_phy_alt_mem_phy_seq_wrapper_&lt;device name&gt;_phy_alt_mem_phy_seq_seq_inst_1453/dgrb/rsc_block#  ** Note: &lt;device name&gt;_phy_alt_mem_phy_seq (dgrb) : gathered resync phase samples DGRB_PHASE_SAMPLES: 00000000111111111111111111111111111111111111111100000000000000000000000000000000#  Time: 304807920 ps Iteration: 8 Instance: /&lt;device name&gt;_tb/ddr2_if_1/u_&lt;device name&gt;/&lt;device name&gt;_controller_phy_inst/&lt;device name&gt;_phy_inst/&lt;device name&gt;_phy_&lt;device name&gt;_phy_alt_mem_phy_&lt;device name&gt;_phy_alt_mem_phy_inst_&lt;device name&gt;_phy_alt_mem_phy_seq_wrapper_seq_wrapper_6153/&lt;device name&gt;_phy_alt_mem_phy_seq_wrapper_&lt;device name&gt;_phy_alt_mem_phy_seq_seq_inst_1453/dgrb/rsc_block#  ** Note: &lt;device name&gt;_phy_alt_mem_phy_seq (dgrb) : data-valid window found successfully.#  Time: 305287240 ps Iteration: 8 Instance: /&lt;device name&gt;_tb/ddr2_if_1/u_&lt;device name&gt;/&lt;device name&gt;_controller_phy_inst/&lt;device name&gt;_phy_inst/&lt;device name&gt;_phy_&lt;device name&gt;_phy_alt_mem_phy_&lt;device name&gt;_phy_alt_mem_phy_inst_&lt;device name&gt;_phy_alt_mem_phy_seq_wrapper_seq_wrapper_6153/&lt;device name&gt;_phy_alt_mem_phy_seq_wrapper_&lt;device name&gt;_phy_alt_mem_phy_seq_seq_inst_1453/dgrb/rsc_block#  ** Note: &lt;device name&gt;_phy_alt_mem_phy_seq (dgrb) : gathered mimic phase samples DGRB_MIMIC_SAMPLES: 1111111111111111111111111111111111111111#  Time: 341911456 ps Iteration: 8 Instance: /&lt;device name&gt;_tb/ddr2_if_1/u_&lt;device name&gt;/&lt;device name&gt;_controller_phy_inst/&lt;device name&gt;_phy_inst/&lt;device name&gt;_phy_&lt;device name&gt;_phy_alt_mem_phy_&lt;device name&gt;_phy_alt_mem_phy_inst_&lt;device name&gt;_phy_alt_mem_phy_seq_wrapper_seq_wrapper_6153/&lt;device name&gt;_phy_alt_mem_phy_seq_wrapper_&lt;device name&gt;_phy_alt_mem_phy_seq_seq_inst_1453/dgrb/trk_block#  ** Note: &lt;device name&gt;_phy_alt_mem_phy_seq (dgrb) : mimic window successfully found.#  Time: 342094848 ps Iteration: 8 Instance: /&lt;device name&gt;_tb/ddr2_if_1/u_&lt;device name&gt;/&lt;device name&gt;_controller_phy_inst/&lt;device name&gt;_phy_inst/&lt;device name&gt;_phy_&lt;device name&gt;_phy_alt_mem_phy_&lt;device name&gt;_phy_alt_mem_phy_inst_&lt;device name&gt;_phy_alt_mem_phy_seq_wrapper_seq_wrapper_6153/&lt;device name&gt;_phy_alt_mem_phy_seq_wrapper_&lt;device name&gt;_phy_alt_mem_phy_seq_seq_inst_1453/dgrb/trk_block#  ** Warning: &lt;device name&gt;_phy_alt_mem_phy_seq (admin) : mode register and generic conflict:#  * generic MEM_IF_DQSN_EN is set to 'disable' DQSN#  * user mode register MEM_IF_MR1 bit 10 is set to 'enable' DQSN#  Time: 342615848 ps Iteration: 8 Instance: /&lt;device name&gt;_tb/ddr2_if_1/u_&lt;device name&gt;/&lt;device name&gt;_controller_phy_inst/&lt;device name&gt;_phy_inst/&lt;device name&gt;_phy_&lt;device name&gt;_phy_alt_mem_phy_&lt;device name&gt;_phy_alt_mem_phy_inst_&lt;device name&gt;_phy_alt_mem_phy_seq_wrapper_seq_wrapper_6153/&lt;device name&gt;_phy_alt_mem_phy_seq_wrapper_&lt;device name&gt;_phy_alt_mem_phy_seq_seq_inst_1453/admin#  ** Note: &lt;device name&gt;_phy_alt_mem_phy_seq (top) : report...#  -----------------------------------------------------------------------#  -- **** ALTMEMPHY CALIBRATION has completed ****#  -- Status:#  -- calibration has : PASSED#  -- PHY read latency (ctl_rlat) is : 16#  -- address/command to PHY write latency (ctl_wlat) is : 4#  -- read resynch phase calibration report:#  -- calibrated centre of data valid window phase : 51#  -- calibrated centre of data valid window size : 40#  -----------------------------------------------------------------------
   i'm sorry for the double post but the original message was too long   thank you for answering

altera_forum · Answer

hi deadalus,  i read your question about 'problem with ddr2 sdram controller', but i don't find a response.  please, if you find a solution for this problem, can you tell me? because i am in the same problem.  good work.

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problem with DDR2 SDRAM controller

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