Honored Contributor
Honored Contributorhere are printout from modelsim transcript:
those warnings is showen only when i run the simulation, there are no warnings when i load the simulation
** Warning: Warning: Value for read_during_write_mode_mixed_ports is not honoured in DUAL_PORT operation mode when output registers are not clocked by clock0 for ram_block_type LUTRAM# Time: 0 ps Iteration: 0 Instance: /<device name>_tb/ddr2_if_1/u_<device name>/<device name>_controller_phy_inst/<device name>_phy_inst/<device name>_phy_<device name>_phy_alt_mem_phy_<device name>_phy_alt_mem_phy_inst_<device name>_phy_alt_mem_phy_read_dp_group_fr_rdp_rdp_per_group_1_rdp_altsyncram_ram_6752# ** Warning: Warning: Value for read_during_write_mode_mixed_ports is not honoured in DUAL_PORT operation mode when output registers are not clocked by clock0 for ram_block_type LUTRAM# Time: 0 ps Iteration: 0 Instance: /<device name>_tb/ddr2_if_1/u_<device name>/<device name>_controller_phy_inst/<device name>_phy_inst/<device name>_phy_<device name>_phy_alt_mem_phy_<device name>_phy_alt_mem_phy_inst_<device name>_phy_alt_mem_phy_read_dp_group_fr_rdp_rdp_per_group_0_rdp_altsyncram_ram_6829# ** Warning: Warning: Value for read_during_write_mode_mixed_ports is not honoured in DUAL_PORT operation mode when output registers are not clocked by clock0 for ram_block_type LUTRAM# Time: 0 ps Iteration: 0 Instance: /<device name>_tb/ddr2_if_1/u_<device name>/<device name>_controller_phy_inst/<device name>_phy_inst/<device name>_phy_<device name>_phy_alt_mem_phy_<device name>_phy_alt_mem_phy_inst_<device name>_phy_alt_mem_phy_postamble_fr_poa_gen_poa_group_1_poa_altsyncram_altsyncram_component_6085# ** Warning: Warning: Value for read_during_write_mode_mixed_ports is not honoured in DUAL_PORT operation mode when output registers are not clocked by clock0 for ram_block_type LUTRAM# Time: 0 ps Iteration: 0 Instance: /<device name>_tb/ddr2_if_1/u_<device name>/<device name>_controller_phy_inst/<device name>_phy_inst/<device name>_phy_<device name>_phy_alt_mem_phy_<device name>_phy_alt_mem_phy_inst_<device name>_phy_alt_mem_phy_postamble_fr_poa_gen_poa_group_0_poa_altsyncram_altsyncram_component_6102# ** Note: Stratix IV PLL was reset# Time: 0 ps Iteration: 8 Instance: /<device name>_tb/ddr2_if_1/u_<device name>/<device name>_controller_phy_inst/<device name>_phy_inst/<device name>_phy_<device name>_phy_alt_mem_phy_<device name>_phy_alt_mem_phy_inst_<device name>_phy_alt_mem_phy_clk_reset_clk_<device name>_phy_alt_mem_phy_pll_full_rate1_pll_5977/altpll_component/stratixiii_altpll/m4# ** Warning: Illegal value detected on input clock.# Time: 100 ns Iteration: 13 Instance: /<device name>_tb/ddr2_if_1/u_<device name>/<device name>_controller_phy_inst/<device name>_phy_inst/<device name>_phy_<device name>_phy_alt_mem_phy_<device name>_phy_alt_mem_phy_inst_<device name>_phy_alt_mem_phy_clk_reset_clk_stratixiii_dll_dll_5708# ** Note: Stratix IV PLL locked to incoming clock# Time: 118784 ps Iteration: 0 Instance: /<device name>_tb/ddr2_if_1/u_<device name>/<device name>_controller_phy_inst/<device name>_phy_inst/<device name>_phy_<device name>_phy_alt_mem_phy_<device name>_phy_alt_mem_phy_inst_<device name>_phy_alt_mem_phy_clk_reset_clk_<device name>_phy_alt_mem_phy_pll_full_rate1_pll_5977/altpll_component/stratixiii_altpll/m4# ** Note: # Time: 131288 ps Iteration: 8 Instance: /<device name>_tb/ddr2_if_1/u_<device name>/<device name>_controller_phy_inst/<device name>_phy_inst/<device name>_phy_<device name>_phy_alt_mem_phy_<device name>_phy_alt_mem_phy_inst_<device name>_phy_alt_mem_phy_seq_wrapper_seq_wrapper_6153/<device name>_phy_alt_mem_phy_seq_wrapper_<device name>_phy_alt_mem_phy_seq_seq_inst_1453/reporting# ** Note: DLL to lock to incoming clock# Time: 2786304 ps Iteration: 9 Instance: /<device name>_tb/ddr2_if_1/u_<device name>/<device name>_controller_phy_inst/<device name>_phy_inst/<device name>_phy_<device name>_phy_alt_mem_phy_<device name>_phy_alt_mem_phy_inst_<device name>_phy_alt_mem_phy_clk_reset_clk_stratixiii_dll_dll_5708# ** Note: <device name>_phy_alt_mem_phy_seq (dgrb) : gathered resync phase samples (for mtp alignment 0) is DGRB_PHASE_SAMPLES: 00000000111111111111111111111111111111111111111100000000000000000000000000000000# Time: 109778864 ps Iteration: 8 Instance: /<device name>_tb/ddr2_if_1/u_<device name>/<device name>_controller_phy_inst/<device name>_phy_inst/<device name>_phy_<device name>_phy_alt_mem_phy_<device name>_phy_alt_mem_phy_inst_<device name>_phy_alt_mem_phy_seq_wrapper_seq_wrapper_6153/<device name>_phy_alt_mem_phy_seq_wrapper_<device name>_phy_alt_mem_phy_seq_seq_inst_1453/dgrb/rsc_block# ** Note: <device name>_phy_alt_mem_phy_seq (dgrb) : gathered resync phase samples (for mtp alignment 1) is DGRB_PHASE_SAMPLES: 00000000000000000000000000000000000000000000000000000000000000000000000000000000# Time: 208693840 ps Iteration: 8 Instance: /<device name>_tb/ddr2_if_1/u_<device name>/<device name>_controller_phy_inst/<device name>_phy_inst/<device name>_phy_<device name>_phy_alt_mem_phy_<device name>_phy_alt_mem_phy_inst_<device name>_phy_alt_mem_phy_seq_wrapper_seq_wrapper_6153/<device name>_phy_alt_mem_phy_seq_wrapper_<device name>_phy_alt_mem_phy_seq_seq_inst_1453/dgrb/rsc_block# ** Note: <device name>_phy_alt_mem_phy_seq (dgrb) : gathered resync phase samples DGRB_PHASE_SAMPLES: 00000000111111111111111111111111111111111111111100000000000000000000000000000000# Time: 304807920 ps Iteration: 8 Instance: /<device name>_tb/ddr2_if_1/u_<device name>/<device name>_controller_phy_inst/<device name>_phy_inst/<device name>_phy_<device name>_phy_alt_mem_phy_<device name>_phy_alt_mem_phy_inst_<device name>_phy_alt_mem_phy_seq_wrapper_seq_wrapper_6153/<device name>_phy_alt_mem_phy_seq_wrapper_<device name>_phy_alt_mem_phy_seq_seq_inst_1453/dgrb/rsc_block# ** Note: <device name>_phy_alt_mem_phy_seq (dgrb) : data-valid window found successfully.# Time: 305287240 ps Iteration: 8 Instance: /<device name>_tb/ddr2_if_1/u_<device name>/<device name>_controller_phy_inst/<device name>_phy_inst/<device name>_phy_<device name>_phy_alt_mem_phy_<device name>_phy_alt_mem_phy_inst_<device name>_phy_alt_mem_phy_seq_wrapper_seq_wrapper_6153/<device name>_phy_alt_mem_phy_seq_wrapper_<device name>_phy_alt_mem_phy_seq_seq_inst_1453/dgrb/rsc_block# ** Note: <device name>_phy_alt_mem_phy_seq (dgrb) : gathered mimic phase samples DGRB_MIMIC_SAMPLES: 1111111111111111111111111111111111111111# Time: 341911456 ps Iteration: 8 Instance: /<device name>_tb/ddr2_if_1/u_<device name>/<device name>_controller_phy_inst/<device name>_phy_inst/<device name>_phy_<device name>_phy_alt_mem_phy_<device name>_phy_alt_mem_phy_inst_<device name>_phy_alt_mem_phy_seq_wrapper_seq_wrapper_6153/<device name>_phy_alt_mem_phy_seq_wrapper_<device name>_phy_alt_mem_phy_seq_seq_inst_1453/dgrb/trk_block# ** Note: <device name>_phy_alt_mem_phy_seq (dgrb) : mimic window successfully found.# Time: 342094848 ps Iteration: 8 Instance: /<device name>_tb/ddr2_if_1/u_<device name>/<device name>_controller_phy_inst/<device name>_phy_inst/<device name>_phy_<device name>_phy_alt_mem_phy_<device name>_phy_alt_mem_phy_inst_<device name>_phy_alt_mem_phy_seq_wrapper_seq_wrapper_6153/<device name>_phy_alt_mem_phy_seq_wrapper_<device name>_phy_alt_mem_phy_seq_seq_inst_1453/dgrb/trk_block# ** Warning: <device name>_phy_alt_mem_phy_seq (admin) : mode register and generic conflict:# * generic MEM_IF_DQSN_EN is set to 'disable' DQSN# * user mode register MEM_IF_MR1 bit 10 is set to 'enable' DQSN# Time: 342615848 ps Iteration: 8 Instance: /<device name>_tb/ddr2_if_1/u_<device name>/<device name>_controller_phy_inst/<device name>_phy_inst/<device name>_phy_<device name>_phy_alt_mem_phy_<device name>_phy_alt_mem_phy_inst_<device name>_phy_alt_mem_phy_seq_wrapper_seq_wrapper_6153/<device name>_phy_alt_mem_phy_seq_wrapper_<device name>_phy_alt_mem_phy_seq_seq_inst_1453/admin# ** Note: <device name>_phy_alt_mem_phy_seq (top) : report...# -----------------------------------------------------------------------# -- **** ALTMEMPHY CALIBRATION has completed ****# -- Status:# -- calibration has : PASSED# -- PHY read latency (ctl_rlat) is : 16# -- address/command to PHY write latency (ctl_wlat) is : 4# -- read resynch phase calibration report:# -- calibrated centre of data valid window phase : 51# -- calibrated centre of data valid window size : 40# -----------------------------------------------------------------------
