Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributorproblem avalon interface for serial multichannel FIR
Hello,
I am trying to implement serial multichannel FIR filter with FIR compiler (2-channel, 15 bit input). I tested different combinations supplying sink_sop an sink_eop signals, but non of them forced filter output to normal operation. The problem is that I can not find specification of how to feed input data of two channels in the case of fully serial FIR arcitecture. Everything works fine with single channel serial filter, but does not with the two channel serial filter (source_sop is never asserted, source_eop behaviour is difficult to explain, source_valid is 0 always). Can anyone provide serial multichannel FIR timing diagrams, or any reference design? This is crusial for our project since fully parallel architecture does not fit in to the seleted FPGA. Thanks for help.4 Replies
Altera_Forumhave you tried taking a look at the MegaCore generated test bench?
- Altera_Forum
Yes I did. But unfortunatelly testbench (vec file) does not contain sop end eop signals. It seems like testbench is generated for the old style FIR interface (prior to Avalon style signals). I even reinstalled Quartus SP2, but testbench still does not describe sink_sop and sink_eop signals.
- Altera_Forum
there isn't an HDL test bench included?
- Altera_Forum
OK, there is something to look at in the output of testbench simulation.
Thank you for now.
