New ContributorPLL unlocked issue when use clock recovery module in Intel DisplayPort Rx IP
Title:
PLL unlocked issue when use clock recovery module in Intel DisplayPort Rx IP
Hi forum members,
We encounter weird behavior when bitec_clkrec module which is a part of DisplayPort Rx IP is to regenerate recover clock via fractional PLL and PLL reconfiguration module around 93.2MHz.
Also, I already post this issue as below.
"DisplayPort Rx IP can't generate stable recover clock in clock recover module."
We suspect that PLL parameters is not suitable. Ex. VCO range, bandwidth setting, charge pump setting and so on.
Especially, we suspect a negative-feedback circuit of PLL is an instability by ex. causing wrong loop filter setting.
[Question]
Q1) Does ArriaV GX have like "Phase Frequency Detector" in "Altera fPLL" module ?
I guess that this answer is yes. But we'd like to confirm it.
Q2) If we set bandwidth parameter as auto, do a fractional PLL with PLL reconfiguration logic automatically change suitable band width setting ?
Q3) How do we consider parameters of loop filter without EXCEL file ? Unfortunately, this IP is protected and automatically update PLL parameters by it self via PLL reconfiguration module.
Q4) Also, how do we consider and/or improve a transient response characteristic ? Because this IP (clkrec module) frequently change PLL parameter to follow a gap between write pointer and read pointer on FIFO by some parameters.
[Note]
This issue occurs our custom board and ArriaV evaluation board too.
Also, it occurs example design too.
Best regards,
