PLL unlocked issue when use clock recovery module in Intel DisplayPort Rx IP

Hello Koji , Let me answer your question first , Q1: Yes , Intel PLL IP do have the PFD, Can you please refer below link Figure 1 PLL Architecture. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/altera_pll.pdf. Q2:If the Bandwdith Preset values set as Auto means IP core choose the best possible bandwidth values to achieve the desired PLL settings. It might be outside the low and high preset range. Q3: Unfortunately no, Internal architecture of loop filter and its math is proprietary to Intel.I would recommend to use Calculator (excel sheet format) provided by Intel. Q4: I am not sure which module transient response you are talking about , Is that for PLL ? Can you kindly Clarify ? Note I am not aware of bitec IP. PLL can loss the lock in many ways , i am unsure about your setting can you let me know which example design you are talking about ? I am trying to think like.. Is it possible to realize your problem through simulation . can you please let me know how i can help you further ? Thank you , regards. Sree