PLL unlocked issue when use clock recovery module in Intel DisplayPort Rx IP

Hi Sree

Thank you for your reply.

I mention to you.

> Q2:If the Bandwdith Preset values set as Auto means IP core choose the best possible bandwidth values to achieve the desired PLL settings. It might be outside the low and high preset range.

Does parameter value of Bandwidth as Auto depend on an initial setting of desired output frequency on GUI of IP catalog of Quatrus even if we use Fractional PLL with PLL reconfiguration logic ?

> Q3: Unfortunately no, Internal architecture of loop filter and its math is proprietary to Intel.I would recommend to use Calculator (excel sheet format) provided by Intel.

Can we estimate these parameters with excel file even if the design use fractional PLL with PLL reconfiguration ?

Unfortunately,

> Q4: I am not sure which module transient response you are talking about , Is that for PLL ? Can you kindly Clarify ? Note I am not aware of bitec IP.

It is for PLL. But many parameters (maybe M value, some C counter value and so on) are calculated by bitec IP.

However, we can observe these parameters (*1) by Signal Tap between calculation logic and Altera PLL reconfiguration logic.

> can you let me know which example design you are talking about ?

> I am trying to think like.. Is it possible to realize your problem through simulation .

I use an example design of Intel DP IP (v17.1) as below on ArriaV Development Kit and HSMC DisplayPort 1.2 Daughter Card.

## IP directory

```

$QUARTUS_ROOT/ip/altera/altera_dp/

```

## ex. Simulation Model

```

$QUARTUS_ROOT/ip/altera/altera_dp/sim_example/av

```

## HMC DisplayPort 1.2 Daughter Card

https://bitec-dsp.com/product/hsmc-displayport-daughter-card/

We'd like to share a part of these parameters which are generated by bitec IP around lock lost timing.

But we can not share them on community forum...

Would you tell me your upload web site or something ?

*)

We can observe them as dprio_writedata (16bit bus), not mgmt_writedata (32bit bus).

[Additional Information]

We suspect bitec clkrec might ignore an inhibited clock frequency range which is defined by pdf and excel file.

Because failed clock frequency range involves this inhibited clock frequency range.

Best regards,