PHY Transmission - Arria II GX

Some PC network cards automatically disregard malformed packets or packets with invalid CRCs, so if you have a problem on the packet it could explain why you don't see it in Wireshark. Have a look at the driver properties and see if you can disable any hardware acceleration, CRC/cheksum calculations or error check. Some drivers also show error counters.

You could also try a loopback test, either by changing a register in the PHY chip or by physically connecting the RX and TX pairs on the network connector. Then you can have a look at the RX signals and check that what you receive is exactly what you sent.

Are you sure that the PHY negotiated correctly a gigabit connection? Are you using a DDR I/O block? In that case are you sure that you use correctly the high and low inputs and are sending the 4-bit words in the right order? Did you properly constrain the RGMII interface and does your design meet all timing requirements?

I looked into this problem further.

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Some PC network cards automatically disregard malformed packets or packets with invalid CRCs, so if you have a problem on the packet it could explain why you don't see it in Wireshark. Have a look at the driver properties and see if you can disable any hardware acceleration, CRC/cheksum calculations or error check. Some drivers also show error counters.

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Viewing netstat through the command console I found that when the Arria II GX development board is transmitting the discard count increases at the same rate of transmission so the packets must be malformed when they get to the computer somehow. I cannot see anyway to turn off CRC/checksum or hardware acceleration but I am reading the reference manual. The NIC is a Broadcom HP NC373i.

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You could also try a loopback test, either by changing a register in the PHY chip or by physically connecting the RX and TX pairs on the network connector. Then you can have a look at the RX signals and check that what you receive is exactly what you sent.

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I have done a loop back test in hardware where I send the exact same bit sequence from input to the output but this programs packets are also recorded as discards.

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Are you sure that the PHY negotiated correctly a gigabit connection? Are you using a DDR I/O block? In that case are you sure that you use correctly the high and low inputs and are sending the 4-bit words in the right order? Did you properly constrain the RGMII interface and does your design meet all timing requirements?

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In terms of the PHY negotiating correctly the Gigabit light turns on which I assumed indicated correct negotiation although I could be wrong.

I'm not sure what you mean by a DDR I/O block but I did try the altddio_out megafunction described in the timing in the altera an477 documentation.

The megafunction never worked so I created the necessary timing by hand using PLL and state machine. These are the timing requirements I followed for the current program I am testing.

I have tried the bit order in both ways for a sample packet but have gotten rx crc errors in both cases. Does the bit order matter if I am not using a DDR I/O block?

What exactly didn't work in the ddr i/o megafunction? Maybe we should start by looking at that.

Did you put timing constrains on the RGMII interface? Does the design meet all timing requirements? he PHY chip can be configured with a 90 degrees clock shift to read/write data at the clock center instead of the edges, by using a special MDIO register.

I followed the RGMII interface specified by Altera more closely and I have a receive and transmit unit working. The ALTDDIO_IN/OUT work very well for this. Also the timing of the TX clock was still shift by 90 degrees.

The only thing that remains is how to make a better basic receive interface? I found that using different equipment preambles vary and even just checking for the preamble itself doesn't work 100% of the time. Do you know of any basic receiver that work very well besides the Altera TSE MAC?