PCIe x4 Root port implementing: Cyclone V vs. Cyclone IV

Question

I want to implement a PCI express root port using a FPGA. My question is simple, It would be enough with an IP_Compiler for PCI Express or it would be necessary a Avalon-MM Cyclone V Hard IP for PCI Express.The issue is about the need of a Cyclone V FPGA or if is enough a Cyclone IV FPGA.

altera_forum · Answer

As long as the FPGA has the PCIE Hard IP core, the core can be configured to either rootport or endpoint regardless of the FPGA families.

Forum Discussion

PCIe x4 Root port implementing: Cyclone V vs. Cyclone IV

1 Reply

Recent Discussions

Can't generate F-Tile Ethernet Hard IP Design Example

Agilex 7 slew rate reconfiguration

Where is High Speed Transceiver Demo Design in FPGA Wiki ?

Avalon-MM Cyclone V Hard IP for PCI Express Intel FPGA IP Soft Reset and Hard Reset

Stratix 10 Transceiver PHY bonding and multiple TX PLL clock inputs (for DisplayPort TX)