PCIe simulation Pipe interface

Dear Intel Support and Expert

I am running Intel PCIe example, in

Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) DMA Interface for PCI Express* Solutions User Guide

section 5.6.2 PIPE interface Signals.

"These PIPE signals are available for Gen1, Gen2, and Gen3 variants so that you can
simulate using either the serial or the PIPE interface. Note that Intel Arria 10 and Intel
Cyclone 10 GX devices do not support the Gen3 PIPE interface."

I am using Arria 10 GX demo board. even it won't support the PIPE interface, I believe the simulation will be supported. am I right?

The simulation runs well when

parameter selrial_sim_hwtcl = 1,

parameter bfm_drive_interface_pipe_hwtcl = 0,

but when I set the

parameter selrial_sim_hwtcl = 0,

parameter bfm_drive_interface_pipe_hwtcl = 1,

I couldn't get the EP LTSSM State change anymore.

if set the simulation run in pipe mode will run faster, let's say X2 or even X3, it will be very helpful to run simulation in this mode.

there isn't much detail in the PCIe DMA manual. could you please give me a link to the instruction to sit the PCIe simulation in PIPE mode.

thank you very much,

David