Forum Discussion

corestar's avatar
corestar
Icon for Contributor rankContributor
2 years ago
Solved

PCIe pld_clk conflicting coreclkout statements

I'm using a Cyclone V GT with PCIe ST core. The app works fine when I drive pld_clk with coreclockout, but fails when I drive pld_clk with a 150 MHz external clock. I used 150 MHz instead of 125 MHz ...
Pcie
  • VenT_Altera's avatar
    VenT_Altera
    2 years ago

    Hi @corestar,


    Thanks for sharing your objective.

    My apologies for the delayed response, I took some time to gather the information.


    In this case, it is suggested that you drive the pld_clk with coreclkout_hip, as using a single clock simplifies timing.


    In the situation that you wish to drive the pld_clk with an other clock source, the following clock frequencies of the clock source could be used:

    1.When coreclkout_hip is 62.5 MHz:

    Try to use 125 MHz, or 250 MHz.

    2. When coreclkout_hip is 125 MHz:

    Try to use 250 MHz.

    Please note that not all frequencies of other clock source within the specified range can be used to drive the pld_clk.


    Thanks.

    Best Regards,

    VenTingT


VenT_Altera's avatar
VenT_Altera
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi @corestar,


Thanks for sharing your objective.

My apologies for the delayed response, I took some time to gather the information.


In this case, it is suggested that you drive the pld_clk with coreclkout_hip, as using a single clock simplifies timing.


In the situation that you wish to drive the pld_clk with an other clock source, the following clock frequencies of the clock source could be used:

1.When coreclkout_hip is 62.5 MHz:

Try to use 125 MHz, or 250 MHz.

2. When coreclkout_hip is 125 MHz:

Try to use 250 MHz.

Please note that not all frequencies of other clock source within the specified range can be used to drive the pld_clk.


Thanks.

Best Regards,

VenTingT


  • corestar's avatar
    corestar
    Icon for Contributor rankContributor
    2 years ago

    Hello @ventt

    Thanks for the info. So apparently both documents are in error. You can use an external clock, but not in the range specified. The 150 MHz should have worked according to the second one. I don't think I could meet timing at 250 Mhz. They may want to update the documentation.

    You mention:

    In this case, it is suggested that you drive the pld_clk with coreclkout_hip, as using a single clock simplifies timing.

    It actually complicates timing for the Application layer, so I assume you mean it simplifies it for the PCIe core?

    In any event, the safest solution is clearly to drive pld_clk with coreclockout_hip. It works.

    Might as well close this one.

    Regards,

    Dave