VenT_AlteraFrequent ContributorJoined 3 years ago420 Posts7 LikesLikes received22 SolutionsView All Badges
ContributionsMost RecentMost LikesSolutionsRe: Stratix V PCIe IP fails upgrade from 21.1 to 25.1 Hi Jesse, Thank you for reaching out to us. The Stratix V PCIe Hard IP (altera_pcie_sv_hip_avmm and altera_pcie_sv_hip_ast) is EOL starting with Quartus 24.1 Std. The recommendation is to use v23.1 Std or earlier to continue using this IP in your design. Please let me know if you have any concerns. Thanks. Best Regards, Ven Re: Looking for a MSI Design Example Hi BXia, I'm glad that your issue is resolved. I will step back and allow the community to assist with any future follow-up questions. Thank you for engaging with us! Best regards, Ven Re: Looking for a MSI Design Example Hi BXia, Thanks for reaching out to us. I have attached the zip file of the Wiki page for you. The FPGA Wiki is currently unavailable; you can still access archived versions using the Wayback Machine. 1. Visit: https://web.archive.org/web/*/http://community.intel.com/t5/FPGA-Wiki/* 2. Browse or search for the specific Wiki page. Thanks. Best Regards, Ven Re: Looking for a MSI Design Example FPGA Wiki zip for Handling PCIe Interrupts attached Re: Error: dut.p0_hip_status has no associated reset. Dear UserID4331231, I hope you are doing well. If there are no further inquiries, I will step back and allow the community to assist with any future follow-up questions. Thank you for engaging with us! Best regards, Ven Re: Error: dut.p0_hip_status has no associated reset. Hi UserID4331231, Thank you for attaching the PD connections screenshots. For debugging purposes, could you export both interfaces from Platform Designer and make the connections at the RTL level? Please ensure that both interfaces have matching signal roles and widths, and check if this connection passes Quartus compilation. Additionally, according to the Quartus Platform Designer User Guide: https://www.intel.com/content/www/us/en/docs/programmable/683609/25-1-1/conduits.html To connect two conduit interfaces inside Platform Designer, the following conditions must be met: The interfaces must match exactly with the same signal roles and widths. The interfaces must be the opposite directions. Clocked conduit connections must have matching associatedClocks on each of their endpoint interfaces. Thanks. Best Regards, Ven Re: Error: dut.p0_hip_status has no associated reset. Hi UserID4331231, May I know if you have any updates? Thanks. Best Regards, Ven Re: Error: dut.p0_hip_status has no associated reset. Hi UserID4331231, May I know if you have any updates on the post? Thanks. Best Regards, Ven Re: Error: dut.p0_hip_status has no associated reset. Hi UserID4331231, Could you please share the screenshots of Platform Designer to show the connections? What are the custom design QCP, MCDMA settings, User Mode, and Interface Type? Thanks. Best Regards, Ven Re: dut.p0_hip_status has no associated reset. Hi UserID4331231, I’ve noticed that this forum case is a duplicate of https://community.altera.com/discussions/ip-and-transceiver/error-dut-p0-hip-status-has-no-associated-reset-/337704. Therefore, I will close this case as a duplication and continue to provide support in the active post. Thanks. Best Regards, Ven