VenT_Altera
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Re: Display port TX SST not working.
Hi PMice Thanks for reaching out. Based on your description, we’ll need additional design configuration details to proceed with debugging. However, I noticed that you’ve submitted a similar debug request in the APS platform, where there is already an active discussion. Since you’re receiving dedicated support from our SME Application Engineer in APS, do you still need assistance on this forum? If this is a duplicate of the APS case, I suggest we close this thread and please continue the discussion in APS. For your reference, you can use our DisplayPort bandwidth calculator tools to verify the total available link bandwidth and ensure it meets the video requirements. DisplayPort IP User Guide: https://docs.altera.com/r/docs/683273/25.3/displayport-ip-user-guide/calculating-video-bandwidth-and-recovered-pixel-clock-frequency Please let me know if you have any concerns. Thanks. Best Regards, Ven Ting17Views0likes2CommentsRe: Agilex-7 AXI MCDMA for PCIe hang
Hi Mikhail_a Thank you for you updates. Your feedback on the AXI interface is noted for future releases. I’ll step back at this point and let the community assist with any follow-up questions. If you have any further questions, please feel free to reach out. Thanks. Best Regards, Ven7Views0likes0CommentsRe: Agilex-7 AXI MCDMA for PCIe hang
Hi Mikhail_a My understanding is that you ran the AXI-MM DMA Example Design application, either perfq_app or mcdma_test, using the provided driver, either Custom or DPDK. When running the application, you observed the failure: Writing 449 bytes to BAS, the host hang and subsequently reset. See Table 57 in the user guide for the application and supported test: https://docs.altera.com/r/docs/817911/25.3.1/axi-multichannel-dma-ip-for-pci-express-user-guide/design-example-overview To run the application of the Example Design, I believe your team has followed the prerequisites steps and commands provided in the user guide: https://docs.altera.com/r/docs/683517/25.3.1/multi-channel-dma-ip-for-pci-express-design-example-user-guide/running-the-design-example-application-on-a-hardware-setup Hence, please provide the log covering the full sequence, from the prerequisites setup up to the point where the errors occur. If my understanding is incorrect, please let me know. Please be advised that I will be out of the office next entire week, beginning Feb 16, and returning on Feb 23. Please expect a delay in response. Thanks. Best Regards, Ven13Views0likes0CommentsRe: Agilex-7 AXI MCDMA for PCIe hang
Hi Mikhail_a I understand that you observed the failure in Example Design as well. Let's focus on the Example Design. Please provide the log from the prerequisites setup to running the application and hit the errors. I'd like to see the exact commands and their output. Which driver (Custom or DPDK) and which AXI-MM DMA test did you perform (perfq_app or mcdma_test)? Please share the detailed steps in the log. Thanks. Best Regards, Ven55Views0likes6CommentsRe: Accessing registers in the PCIE IP beyond MCDMA using system console
Hi Dhiraj Thank you for the updates. I’m looking into your additional questions and will get back to you as soon as possible. Please be advised that I will be out of the office next entire week, beginning Feb 16, and returning on Feb 23. Please expect a delay in response. Thanks. Best Regards, Ven34Views0likes1CommentRe: Agilex-7 AXI MCDMA for PCIe hang
Hi Mikhail_a Thank you for your reply. Since you are using your own driver and application, to isolate whether the issue is software or hardware, please run our Example Design on your board. Port the Example Design to your platform and run the accompanying application. Follow the steps in the user guide to generate Example Design and run the application. https://docs.altera.com/r/docs/817911/25.3.1/axi-multichannel-dma-ip-for-pci-express-user-guide/functional-description?tocId=ak5zOaugZ0426etSxKRO0Q You may generate the AXI-MM DMA Example Design and use the Custom or DPDK driver to perform the perfq_app or mcdma_test: AXI-MM DMA test. Please share your test results. Also, could you share the design goal for your implementation? If MCDMA is not required, you might consider using BAM + BAS (user mode) to simplify the design. Thanks. Best Regards, Ven34Views0likes7CommentsRe: agilex 7 Platform Designer PIO 2x8
Hi xiaohao I am glad that your issue has been resolved. We’ll go ahead and close this forum thread. If you need further assistance or encounter any new issues, please open a new thread. We’re happy to help. Thank you for engaging with us! Thanks. Best Regards, Ven11Views0likes0Comments