VenT_Altera
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Re: Error: dut.p0_hip_status has no associated reset.
Hi UserID4331231, Thank you for attaching the PD connections screenshots. For debugging purposes, could you export both interfaces from Platform Designer and make the connections at the RTL level? Please ensure that both interfaces have matching signal roles and widths, and check if this connection passes Quartus compilation. Additionally, according to the Quartus Platform Designer User Guide: https://www.intel.com/content/www/us/en/docs/programmable/683609/25-1-1/conduits.html To connect two conduit interfaces inside Platform Designer, the following conditions must be met: The interfaces must match exactly with the same signal roles and widths. The interfaces must be the opposite directions. Clocked conduit connections must have matching associatedClocks on each of their endpoint interfaces. Thanks. Best Regards, Ven0Views0likes0CommentsRe: dut.p0_hip_status has no associated reset.
Hi UserID4331231, I’ve noticed that this forum case is a duplicate of https://community.altera.com/discussions/ip-and-transceiver/error-dut-p0-hip-status-has-no-associated-reset-/337704. Therefore, I will close this case as a duplication and continue to provide support in the active post. Thanks. Best Regards, Ven2Views0likes0CommentsRe: "No Video Input" message on the monitor running Display port design example for Arria 10 SX SoC
Hi valentyns, As there are no further inquiries, I will step back and allow the community to assist with any future follow-up questions. Thank you for engaging with us! Best regards, Ven4Views0likes1CommentRe: "No Video Input" message on the monitor running Display port design example for Arria 10 SX SoC
Hi valentyns, The official Arria 10 design example is for the Arria 10 GX Dev Kit using the Bitec DP daughter card. There is a design example for Arria 10 DP using the onboard connector for TX only, available in the FPGA Design Store. You may try out this design example. Please note that the Quartus version provided is 16.0.0, so you will need to perform an IP upgrade when migrating the design to QPDS Pro v25.1. Additionally, the design example targets the Arria 10 Dev Kit, so you will need to migrate it to the SoC board that you are using. https://www.intel.com/content/www/us/en/design-example/749044/intel-arria-10-fpga-displayport-using-onboard-connector-tx-only-design-example.html Thanks. Best Regards, Ven9Views0likes4Comments