VenT_Altera
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Re: Agilex 5 A5ED043AB23AI2V with pcie and usb 3.1 design issue
Hi chandu_12867 As there have been no recent updates on this thread, we will proceed to transition it to community support for now. Should you need any further assistance, please feel free to open a new thread, and we will be glad to help. Thanks. Best Regards, Ven5Views0likes0CommentsRe: Accessing registers in the PCIE IP beyond MCDMA using system console
Hi Dhiraj Thank you for your update and for sharing your resolution with the community. I’m glad to hear that your initial issue has been resolved. I will transition this thread to community support. If you have a new question, feel free to open a new thread to get support from Altera experts. Thanks. Best Regards, Ven6Views0likes0CommentsRe: Accessing registers in the PCIE IP beyond MCDMA using system console
Hi Dhiraj My sincere apologies for the delayed response and thank you for your patience. I was tied up with higher-priority tasks and missed following up on your query. Regarding your question: Yes — when using System Console, access is through the HIP Reconfig AXI-Lite Slave interface. However, this interface primarily exposes the PCIe HIP registers. It does not provide unified access to both PCIe and MCDMA registers. PCIe registers: Accessible via the HIP Reconfig AXI-Lite interface. MCDMA registers: Typically accessed through the MCDMA CSR interface (via its AXI-Lite slave), or through software drivers from the host. The behavior you observed (CSR Lite interface responding regardless of address range) is expected if the address decoding is not correctly mapped to the HIP register space. Internally, access to MCDMA registers is through its own CSR interface, not through the HIP interface. Apologies again for the inconvenience caused. Please let me know if you would still like to continue debugging this, I am happy to assist further. Thanks. Best Regards, Ven8Views0likes0CommentsRe: Agilex 5 A5ED043AB23AI2V with pcie and usb 3.1 design issue
Hi chandu_12867 Did you attach your modified design? I could not find any attachments—only the link to the reference design. Yes, the link is for Agilex 5 E-Series ES device. Please review and try the recommendations provided in my previous reply on your side. Thanks. Best Regards, Ven15Views0likes0CommentsRe: PCIe not working (no enumeration) Agilex™ 5 FPGA E-Series 065B Modular Development Kit
Hi SidL As some time has passed since the last update on this thread, we will proceed to transition it to community support. If you need further assistance, please feel free to open a new thread to receive support from Altera experts. Thank you for your understanding. Best Regards, Ven10Views0likes0CommentsRe: Agilex 5 A5ED043AB23AI2V with pcie and usb 3.1 design issue
Hi chandu_12867 Thank you for reaching out to us. My apologies for the delayed response. I will review your questions regarding the PCIe IP. To better understand your issue, could you please provide the following details: Which dev kit are you using for the device with OPN: A5ED065BB32AE4SR0 (This is an ES device). Is this an Altera Dev Kit. Please share the Dev Kit link or user guide. What design example are you using for PCIe Gen4x4 and HPS USB3.1 combination? I am not aware of this design reference. Please share the link or the design example variant name. Quartus version used. If possible, please share the design. We need these details to further analyze the issue. Based on your description and the fitter errors, here are a few points to consider: Moving from the B32A package to the B23A package reduces available resources and device density. Moving from A5E065 to A5E043 reduces the GTS transceiver banks. The fitter error indicates that the tool failed to place internal HPS nodes. When migrating from an ES device (or different OPN/package) to a production device, it is recommended to carefully upgrade the IP. You may try regenerating the HPS IP from scratch for the B23A package (the production device) to avoid carrying over previous parameter settings. To rule out any density limitations with the B23A package, you may also try compiling the same design with the B32A package again. Please let me know if you have any updates. Thanks. Best Regards, Ven12Views0likes4CommentsRe: PCIe not working (no enumeration) Agilex™ 5 FPGA E-Series 065B Modular Development Kit
Hi SidL Thank you for reaching out. We apologize for the delayed response. Your post was routed to a different queue initially, which caused it to be missed. Could you please let us know if your issue has been resolved, or if you still need support on this forum post? We apologize for any inconvenience caused. Thanks. Best Regards, Ven19Views0likes0Comments