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BeJamIn's avatar
BeJamIn
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21 days ago

IP components used in the design have conflicting settings. Intel PCIE Ftile MCDMA

I generated a 4x4 PCIE MCDMA using the ip designer using quartus 25.3.0.109 from the example design from https://altera-fpga.github.io/rel-25.1/embedded-designs/agilex-7/m-series/pcie_rp/ug-pcie_rp-a...
Programmable Logic Device
BeJamIn's avatar
BeJamIn
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18 days ago

Sorry yes I got it to work. I wanted to avoid removing all my connections so I went in to the xml and removed everything that had "core4" in it, and it built fine. It seems IP designer leaves in xml when converting between 4x4 and 1x16.

VenT_Altera's avatar
VenT_Altera
Icon for Frequent Contributor rankFrequent Contributor
15 days ago

Hi BeJamIn 

Thank you for the updates.
Yes, that can be used as a workaround if you prefer not to remove the existing connections.
However, the safest path is the approach to remove current MCDMA IP and regenerate a fresh MCDMA IP when changing the mode configuration to ensure all the generated files are all clean and correct.

Since the issue has been resolved, I will transition this thread to the community. If you have any new questions, please feel free to open a new thread and the Altera experts will be happy to assist.

Thanks.
Best Regards,
Ven