Forum Discussion
PCIe pld_clk conflicting coreclkout statements
- 2 years ago
Hi @corestar,
Thanks for sharing your objective.
My apologies for the delayed response, I took some time to gather the information.
In this case, it is suggested that you drive the pld_clk with coreclkout_hip, as using a single clock simplifies timing.
In the situation that you wish to drive the pld_clk with an other clock source, the following clock frequencies of the clock source could be used:
1.When coreclkout_hip is 62.5 MHz:
Try to use 125 MHz, or 250 MHz.
2. When coreclkout_hip is 125 MHz:
Try to use 250 MHz.
Please note that not all frequencies of other clock source within the specified range can be used to drive the pld_clk.
Thanks.
Best Regards,
VenTingT
Hi @corestar,
We would recommend users drive the pld_clk with coreclkout_hip.
If you wish to drive the pld_clk at a higher speed, it is recommended to do it in the user logic in the application layer but not directly to the FPGA.
Regarding the pld_clk signal description of the two documents, I'm checking it with the internal team. It will take some time for the checking.
Thanks.
Best Regards,
VenTingT
Hello @ventt
My main motivation was avoiding a few clock domain crossings as opposed to higher clock speed.
Since the design works fine when I drive pld_clk with coreclockout_hip, but fails otherwise, I have to assume it is a requirement. But the first guide mentioned went into great detail on the nature of the external clock, so it seemed like they knew what they were talking about.
It will be interesting to here the resolution.
Thanks,