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Altera_Forum's avatar
Altera_Forum
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9 years ago

PCIe IO BAR's limited to "Legacy Endpoints"

I am looking to define an EP with a BAR defined as IO instead of memory inorder to test the IO / CNFG PCI ordering rules .

I thought it would be as easy as going into an existing design and re-defining the BAR type ... It appears the IO BAR type is only supported by "Legacy Endpoints" .

Does anyone know why this is or how to get around it ?

Thanks, Bob.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    IO style endpoints aren't really supported in PCIe. They only exist so that legacy PCI cards can be attached via a PCIe to PCI bridge. I wouldn't be at all surprised to find out they don't work. I wouldn't be upset about it either. It's basically legacy garbage that should be ignored in a modern design.

  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    --- Quote Start ---

    IO style endpoints aren't really supported in PCIe. They only exist so that legacy PCI cards can be attached via a PCIe to PCI bridge. I wouldn't be at all surprised to find out they don't work. I wouldn't be upset about it either. It's basically legacy garbage that should be ignored in a modern design.

    --- Quote End ---

    Thanks Galfonz.

    I'm not particularly interested in IO and understand the point you make but I am interested in testing ordering rules for IO and Configuration Writes / Reads per the specified rules since IO and Configuration are handled differently ... Since IO and Configuration are treated the same with respect to ordering , I thought IO would be easier to implement.

    If it is't easy to implement with the hard PCIe IP I have access to ... then I will look to the Keysight and LeCroy Exerciser cards that I have access to.
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    It's definitely going to be easier to use something that will generate the kind of traffic you are interested in and a monitor to view what the responses are than it would be to implement something with an FPGA, hard IP or soft.