hi, i use the civgx30 on my board to utilize the pciex4 hardip. but unfortunately,i connect (slot lane0) to (fpga lane3),and (slot lane1) to (fpga lane2),and (slot lane2) to (fpga lane1), and (slot lane3) to (fpga lane0). so ,my board cant work. software i use the quartus 11.1. do anyone have some idea? thanks!

I just came across your post because I was reviewing documents about the lane reversal feature of the PCIe hard IP core for Cyclone V. According to the PCIe user guide, Cyclone IV hard IP also does support lane reversal. But does it actually work, and is it automatical or must it be configured? Unlike Arria V, that has a pin assignment perfectly ordered for a PCIe card, Cyclone V needs lane reversal if you don't want to cross all Rx and Tx pairs in a 4 lane design.

Simply pin-out the FPGA correctly (0 to 0, 1 to 1, 2 to 2, 3 to 3). The Ip will functionally then perform Lane Reversal Automatically for you. This is a built in required feature of PCIe.

Thank you for the clarification. I got the same answer from Altera support in the meantime, also regarding keeping the regular PCIe pinout in Quartus (which I didn't consider before). This is good news, because it allows a straightforward routing of a standard PCIe x4 interface.

--- Quote Start --- Simply The Ip will functionally then perform Lane Reversal Automatically for you. This is a built in required feature of PCIe. --- Quote End --- What do You mean - pin-out the FPGA correctly (0 to 0, 1 to 1, 2 to 2, 3 to 3)? According to the attached picture 0 to 0, 1 to 1, 2 to 2, 3 to 3 can be both for Plane reversal and No plane reversal. How exactly is to make plane reversal for Cyclone IV GX with PCIe x 4 Hard IP? Apparently that has to be done in *.qsf file, in Pin Planner or where?

pcie hardip Lane Reversal | Altera Community

12 Replies

Altera_Forum
Honored Contributor
12 years ago
It seems, that for Altera support terms "route" and "connect" mean different things.
What is wrong then with what did the topicstarter: (slot lane0) to (fpga lane3),and (slot lane1) to (fpga lane2),and (slot lane2) to (fpga lane1), and (slot lane3) to (fpga lane0)?
If this is the way he "routed" the PCB, then it is correct?
But if this is the way he "connected" in Quartus pin assignment, then it is not correct?
Did I understand correctly the answer from Altera support?
leozzz
New Contributor
4 years ago
one more question here: I do not understand why the x4 core lane reversal has to do with the slot size.

does this means we have to get to know the root complex (link partner) size slot size before we route the reversed lanes on end point size PCB?

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pcie hardip Lane Reversal

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