Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributorpcie hardip Lane Reversal
hi, i use the civgx30 on my board to utilize the pciex4 hardip. but unfortunately,i connect (slot lane0) to (fpga lane3),and (slot lane1) to (fpga lane2),and (slot lane2) to (fpga lane1), and (slo...
Altera_ForumHonored Contributor
Honored ContributorIt seems, that for Altera support terms "route" and "connect" mean different things.
What is wrong then with what did the topicstarter: (slot lane0) to (fpga lane3),and (slot lane1) to (fpga lane2),and (slot lane2) to (fpga lane1), and (slot lane3) to (fpga lane0)? If this is the way he "routed" the PCB, then it is correct? But if this is the way he "connected" in Quartus pin assignment, then it is not correct? Did I understand correctly the answer from Altera support?
