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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

pcie hardip Lane Reversal

hi, i use the civgx30 on my board to utilize the pciex4 hardip. but unfortunately,i connect (slot lane0) to (fpga lane3),and (slot lane1) to (fpga lane2),and (slot lane2) to (fpga lane1), and (slo...
leozzz's avatar
leozzz
Icon for New Contributor rankNew Contributor
4 years ago

one more question here: I do not understand why the x4 core lane reversal has to do with the slot size.

does this means we have to get to know the root complex (link partner) size slot size before we route the reversed lanes on end point size PCB?