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Altera_Forum
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15 years ago

PCIe Hard Micro related Signals

Hi All about the DUT transmitter interface to PCIe_HM. When DUT transmits data on transaction interface, which signal can be used to indicate that lower word is valid or not? The signal rx_st_b...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Byte enables are part of the TLP, there is a »first DW BE« and a »last DW BE« field in the header. Look at a Section called » First/Last DW Byte Enables Rules« in your PCI Express Specification.

rx_st_be0 is an optional convenience signal introduced by Altera for received packets only, you could equally decode and use first/last DW Byte Enables of the received TLP. Upon transmission you can only set byte enables based on the mentioned TLP fields.