PCIe Hard IP Configuration Question

I'm simulating the SOPC variation of the testbench that the PCIe Compiler creates so that I can see how the BFM is configuring the PCIe IP. I see several testbench messages like "INFO: 37192 ns EP PCI Express Device Control Register (0010)" that tell me the RP has accessed the EP Control Register space but I don't see any activity on the Avalon MM Bus signals. When I get to the point in the testbench where the memory is being accessed I again see testbench messages that this is happening and then I do see Avalon MM Bus signal activity. Why don't I see any Avalon Bus activity during the configuration?