PCIe design reference recommendation (Cyclone 10 GX)

Hi Derek,

Can I understand it in this way: Before starting the DMA transfer, the computer driver needs to edit this translation table according to the DMA descriptor table first. In this way, during the DMA transfer, the bridge can convert the avalon-mm address passed in through the txs interface into the physical address of the memory applied by the computer driver for DMA.
>> Yes, your understanding is correct. Before initiating a DMA transfer, the computer driver typically needs to configure the address translation table within the PCI Express Avalon-MM bridge. This configuration ensures that the addresses used in the DMA descriptor table are correctly mapped to the physical addresses in the system memory.

The board I designed is a Gen2x1 PCIe board. If I generate an IP core of "Avalon-MM with DMA, Gen2x4", can it be used for my board?
>> Theoritically, you can use a Gen2x4 IP core with a Gen2x1 board, the system will operate with only one lane active, limiting the bandwidth to that of a Gen2x1 configuration. Make sure to adjust any settings in the IP core or driver to reflect the actual lane count supported by your hardware.

Regards,
Wincent_Altera