PCIe design example

Question

Hi,We have A10 GX devkit with us and I want to get started with PCIe testing and example designs.I have windows 10 Host PC. Please suggest on how do I get started with PCIe?Example design is good way to start with or any other things I can get to try it before to have fair understanding.Is there any example design which I can run and is supported in Windows 10, I could only see most designs with Linux. Some designs it does mention as windows but doesn't specify which windows version. Can you pls confirm?

wincent_altera · Answer

Hi,You can try to use AN708 that is available for Windows.https://www.intel.com/content/www/us/en/design-example/714463/arria-10-an708-pcie-gen3x8-avmm-dma-with-external-memory.htmlWindows Software64-bit Windows driver and application.In the package, there is a word document which explains how to install the driver,what additional software needs to be installed, and how to run the application.You may try to run it, if there have any problem, feel free to reach back to us.Regards,Wincent_Intel

wincent_altera · Answer

Hi,

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

Else I would like to have your permission to close this forum ticket

Regards,

Wincent_Intel

p/s: If any answer from the community or Intel Support is helpful, please feel free to give the best answer or rate 9/10 survey.

vadi96 · Answer

Thanks wchaih for the suggestion. I want to understand clocking structure to PCIe hard IP. What should be the frequency of the clock and how it has to be connected. Can you help me on this? Thanks

wincent_altera · Answer

Hi ,The frequency of the clock, you may refer to the user guidehttps://cdrdv2-public.intel.com/666787/ug_a10_pcie_avmm-683724-666787.pdfBut it depends on which design that you are using either is AVST, AVMM , MCDMA ?Regards,Wincent_Intel

vadi96 · Answer

Thanks for the suggestion, i will go through respective user guide on clockin. Thanks.https://www.intel.com/content/www/us/en/design-example/714459/intel-arria-10-fpga-an690-pcie-3-0-x8-avalon-memory-mapped-direct-memory-access-dma-with-on-chip-memory-design-example.htmlI have one more doubt regarding this example design, I am trying out this design in Quartus 23.4. I see Quartus synth errors wrt some commands in QSF. What is it intended for? Is it okay/safe comment those  lines (attached below) and proceed further?set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -riseset_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fallset_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -riseset_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall

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PCIe design example

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