Forum Discussion
New ContributorPCIe design example
Regular ContributorHi,
I wish to follow up with you about this case.
Do you have any further questions on this matter ?
Else I would like to have your permission to close this forum ticket
Regards,
Wincent_Intel
p/s: If any answer from the community or Intel Support is helpful, please feel free to give the best answer or rate 9/10 survey.
New Contributor- Wincent_Altera
Hi ,
The frequency of the clock, you may refer to the user guide
https://cdrdv2-public.intel.com/666787/ug_a10_pcie_avmm-683724-666787.pdf
But it depends on which design that you are using either is AVST, AVMM , MCDMA ?Regards,
Wincent_Intel- Vadi96
Thanks for the suggestion, i will go through respective user guide on clockin. Thanks.
https://www.intel.com/content/www/us/en/design-example/714459/intel-arria-10-fpga-an690-pcie-3-0-x8-avalon-memory-mapped-direct-memory-access-dma-with-on-chip-memory-design-example.htmlI have one more doubt regarding this example design, I am trying out this design in Quartus 23.4. I see Quartus synth errors wrt some commands in QSF. What is it intended for? Is it okay/safe comment those lines (attached below) and proceed further?
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall- Wincent_Altera
Hi,
It is timing fail, if your project requirement does not need strict timing.
As long as the design can be link up correctly, then it can be ignoreRegards,
Wincent_Intel
