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Altera_Forum
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17 years ago

PCI Express:Max_payload_size and lane width

i have design a X4 pcie endpoint device based on Quartus pci express ip V7.2. when i plug the device to the x16 pice slot of my dell optiplex 620 host, the device can only be recognized as an ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

You are welcome. I think most standard issue OS and chipset support only 128 bytes payload. So, there is no easy way to bypass that constraint. On other hand, you can try to increase max_outstanding_read_size and chained DMA operation (if not already) to improve your performance.