Honored ContributorHello,
I've downloaded and installed the MegaCore IP Library and i've simulated my design using two cores: Reed Solomon Decoder and Viterbi Decoder and now I want to perform the time-limited hardware evaluation on my board. But the feature isnt there by default. Can someone tell me to install the feature of hardware evaluation. Wht must be the next step? Thankyou
Honored ContributorIt's used automaticly for IPs not covered by your installed license. Or do you get an error when trying to compile a design that uses the IPs?
Honored ContributorYes there are errors when i compile. What files shud I include in the Quartus project before compilation of the IPs. One more thing there is no folder such as "lib_time_limited" in the onstallation folder of the MegaCore IP library!!!
Honored ContributorI get the following error:
Error: Node instance "auk_vit_par_top_atl_inst" instantiates undefined entity "auk_vit_par_top_atl"Honored ContributorI didn't use the said IPs, but generally the open core evaluation functionality is provided by the *.ocp design files in connection with the core. They are also mentioned in some MegaCore user manuals. But it may be a special issue related to the viterbi core.
Honored ContributorThe issue isn't with OpenCore Plus. You simply can't compile the design period because Quartus II isn't finding all the files for the IP core. This is a periodic problem with Altera IP. More recently, they've switched to using a special file called a QIP file that tells Quartus II where to find the source files for the IP core. I usually workaround the problem by adding the lib directory for the IP core to my User Libraries path.
