Honored Contributorhi, after using Quartus II 7.0 full version and the NIOS 2 open core plus for a week. I could not synthesize my NIOS 2 system since the cpu.v is a time-limited files. do you guys have this problem?
I think I was allowed to use this open core and download the sof file to FPGA and evaluate it as long as my JTAG USB blaster is connected to my PC.
Honored ContributorOne option would be to rebuild the system again and see if it starts working.
It should just keep working but maybe your time limited license is about to run as as well? File an SR with the factory and ask them the same question. It does sound odd to me.Honored ContributorI agree completely, this should not happen.
Try creating a new project from the scratch or copy standard reference design to some other location and try compiling the same. The OCP evaluation should work without any problem.Honored Contributorthis is the error message:
Info: Running Quartus II EDA Netlist Writer Info: Version 7.1 Build 156 04/30/2007 SJ Full Version Info: Processing started: Tue Jul 24 11:32:08 2007 Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off niosbase -c niosbase Error: Can't generate netlist output files because the file "C:/PCIE/niosbase/cpu.v" is an OpenCore Plus time-limited file Error: Can't generate netlist output files because the file "C:/PCIE/niosbase/cpu.v" is an OpenCore Plus time-limited file Error: Can't generate netlist output files because the file "C:/PCIE/niosbase/cpu.v" is an OpenCore Plus time-limited file Error: Can't generate netlist output files because the file "C:/PCIE/niosbase/cpu.v" is an OpenCore Plus time-limited file Error: Quartus II EDA Netlist Writer was unsuccessful. 4 errors, 0 warnings Info: Allocated 118 megabytes of memory during processing Error: Processing ended: Tue Jul 24 11:32:10 2007 Error: Elapsed time: 00:00:02 Error: Quartus II Full Compilation was unsuccessful. 4 errors, 112 warningsHonored ContributorI created a new system with the spec and I got the same problem. Why me!!!!!?????
Honored ContributorDo you use to fake or crack license ?
Sometime, Crack License use.....show to error message...Honored ContributorHi Dimo
I have seen this before with opencore / opencore plus. The problem you are seeing is because you have 3rd party simulation enabled (hence the EDA netlist writer is running, which is where the error is being seen). Opencore plus does not allow creation of simulation netlists. Try turning this option off under settings->eda tool settings->simultion. (select no simulator) If this still doesn't work try removing the PCIE. CheersHonored ContributorOpenCore Plus allows you to run an IP Functional Simulation model in any VHDL or Verilog simulator. It does not allow you to simulate at the gate level.
There was a problem found in Quartus 7.1 that exhibited strange behavior for OpenCore Plus. There is a patch available. See http://www.altera.com//support/kdb/solutions/rd07272007_148.htmlHonored ContributorThe patch is the answer.
Install Sp1, then the patch. An error occored with the Open Core Plus stuff. By the way, you are using 7.1, not 7.0 as you initially indicated. Hope all is well.Honored Contributorproblem resolved by unchecking the EDA netlist writer option in simulation setting. My mistake.
Honored ContributorI am using Quartus 2 V8.0. I do not have any of the simulators in the EDA tools and the patch that is available for V7.1 and it doesnt install on the V8.0.
