Forum Discussion
Altera_Forum
Honored Contributor
15 years ago --- Quote Start --- Have a look at the RTL viewer and see how your two components are interconnected. You should be able to access those signals from both Modelsim and the Quartus simulator. Learning to use Modelsim could be a good idea though, as the Quartus simulator will soon become obsolete. If those interconnection signals were indeed synthesized away, it means that Quartus detected that they were never changing. There may be a configuration problem one one of the two cores... --- Quote End --- Hi, I have some problems with the simulator of the FFT_core_V90 .I have got the data and I am sure they are right.But the source_valid is always keep low. I am using the Quartus II 9.0. I hope you can help me to find what cause the result.