Forum Discussion
Altera_Forum
Honored Contributor
16 years agoHave a look at the RTL viewer and see how your two components are interconnected. You should be able to access those signals from both Modelsim and the Quartus simulator.
Learning to use Modelsim could be a good idea though, as the Quartus simulator will soon become obsolete. If those interconnection signals were indeed synthesized away, it means that Quartus detected that they were never changing. There may be a configuration problem one one of the two cores...