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The SOPC system looks good... It would be interesting to see the signals between the channel adapter and the fft to see what's really happening. They are more difficult to catch, as you must go a bit deeper in the SOPC system to look for them.
Shouldn't the clk_ena_to_the_my_fft_0 be 1?
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Thanks for pointing out the "clk_ena_to_the_my_fft_0" mistake. I have just changed that, but the result is the same: "source_eop' still raises without the rising of "source_sop", hence the error signal still has the value "01"...
Exactly, I am going to debug by looking at those signals between the components. I am going to try to use the Modelsim. can you take a look at my post over here:
http://www.alteraforum.com/forum/showthread.php?p=79930#post79930 I am having problems for using the testbench I exported from Quartus II.
I really appreciate for your precious time!
Best regards
Honored Contributor
