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JWall40's avatar
JWall40
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5 years ago

No output from FFT IP

I am trying to perform a FFT on a single 1024 sample frame, using streaming architecture. However, I cannot get source_valid to go high or any output. Here's my signal tap

4k samples

Start of packet

End of Packet

  • I am asserting rst_n, sink_valid and source ready and keeping them asserted.
  • source_ready goes high, indicating the FFT is ready to accept data
  • I am passing 1024 samples into sink real between sop and eop pulses
  • No source or sink errors

Why am I not seeing any data or source_valid change on the 2048th signal tap sample?

Thanks for reading,

kind regards

Jack

7 Replies

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi Jack,

    As I understand it, you observe issue with FFT seems not having any output after you feed in the data. You are running in SignalTap. For your information, as I look into your screenshots, I notice that the "clk" seems to be remain asserted without toggling. Not sure if this is the clock for the FFT IP core? If yes, you might need to look into this to check if there is any valid clock signal into the FFT IP? thank you very much.

    Apart from the clock, the other signals ie valid, ready, SOP, EOP seems to have no anomaly.

    Please let me know if there is any concern. Thank you.

    Best regards,

    Chee Pin

    • JWall40's avatar
      JWall40
      Icon for New Contributor rankNew Contributor
      5 years ago

      Hi Chee,

      The clock looks like that because I am using the same clock to sample with in signal tap. I've added a new clk at 2x the FFT clock speed to use with signal tap which shows the fft clock to be running as expected.

      I've modified the design to us an NCO IP generating the source signal and so that it constantly runs regardless of any lack of output. I've attached the archive of this project to the reply below. I would really appreciate it if you could take a look at it for me. I've even tried using a different PC and installing a different version of quartus, but still get the same problem. I also get the same problem (no output, source valid never gets asserted) when I try using it in buffered burst mode.

      Any help with this is very much appreciated.

      Many thanks

      Jack

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,

    Thanks for sharing the QAR. As I look into the design, I understand that you are using Max10 and there is a NCO feeding data to FFT. You are using counters to control the SOP/EOP.

    When look into your FFT configuration, I notice the following:

    1. Length = 128. If I remember it correctly, you mentioned that you are feeding 1024 samples. Not sure if this is something expected? If not, try setting to 1024.

    2. Representation = Block Floating Point. Can you try with Fixed Point.

    Please let me know if there is any concern. Thank you.

    Best regards,

    Chee Pin

    • JWall40's avatar
      JWall40
      Icon for New Contributor rankNew Contributor
      5 years ago

      It works!!!! Thank you very much :)

      The length was intentional, I reduced it so I could see more cycles using signal tap without using up all my resources.

      Changing to variable streaming and then fixed point solved the problem. Why does fixed point representation solve the problem? Is it something to do with the Max10 family?

      Many thanks and best regards

      Jack

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,

    Glad to hear that you have managed to resolve the issue. Regarding your inquiry on the fixed point, for your information, fixed point format can take in the input to FFT directly and treat it as normal binary data. If you are selecting other format ie single floating point, your data input need to comply or follow the required format. Based on your observation, I believe it is due to the data formatting which lead to the no output issue.

    Please let me know if there is any concern. Thank you.

    Best regards,

    Chee Pin

  • omerc's avatar
    omerc
    Icon for New Contributor rankNew Contributor
    3 years ago

    Dear @CheePin_C_Intel ,

    I did not fully get the implications of using the block floating point and fixed point and the difference of the consequences of using them. I get a working and erroneous implementation by using the fixed point variable streaming and block floating point streaming configurations of the FFT IP. the problem is explained in the following thread:

    https://community.intel.com/t5/FPGA-Intellectual-Property/FFT-Intel-FPGA-IP-altera-fft-ii-unexpected-source-error-missing/m-p/1406713#M26100

    Do you have any idea why would block floating point could generate an missing_sop error in such a design where fixed point do not?

    I would much appreciate if you can help me with this issue.

    Best Regards