New Contributor
Regular ContributorHi Jack,
As I understand it, you observe issue with FFT seems not having any output after you feed in the data. You are running in SignalTap. For your information, as I look into your screenshots, I notice that the "clk" seems to be remain asserted without toggling. Not sure if this is the clock for the FFT IP core? If yes, you might need to look into this to check if there is any valid clock signal into the FFT IP? thank you very much.
Apart from the clock, the other signals ie valid, ready, SOP, EOP seems to have no anomaly.
Please let me know if there is any concern. Thank you.
Best regards,
Chee Pin
New ContributorHi Chee,
The clock looks like that because I am using the same clock to sample with in signal tap. I've added a new clk at 2x the FFT clock speed to use with signal tap which shows the fft clock to be running as expected.
I've modified the design to us an NCO IP generating the source signal and so that it constantly runs regardless of any lack of output. I've attached the archive of this project to the reply below. I would really appreciate it if you could take a look at it for me. I've even tried using a different PC and installing a different version of quartus, but still get the same problem. I also get the same problem (no output, source valid never gets asserted) when I try using it in buffered burst mode.
Any help with this is very much appreciated.
Many thanks
Jack
New ContributorHere's the Project file. Many thanks
