no free buffers for rx

Did you use the "reassign base address" option afterwards? It should move all your components addresses again, and hopefully solve the overlap problems.

I see you have an Avalon Clock crossing bridge too, try to lock it to address 0 too if you still have problems. I think it is the one responsible for the last error (ddr2_bot.s1 appears at more than one address).

Also check that you don't have any component with an Avalon Slave interface that is connected to both sides of a pipeline bridge. This could confuse SOPC builder.

Thanking you for your prompt reply,

yes, i have assign the base address option afterword, I am using Quartus 11.0 SP1, it has assign base address, rather then reassign base address (see windscreen), i hop both things are same.

what is the role of descriptor memory in this case, i connect it's read and write port to SGDMA descriptor read and write port.

With Regards

kaushal

Yes that's the right name. Sorry about that.

Ensure that your components are only connected behind the pipeline/clock crossing bridges. If as an example you have:

CUP Data master > pb_cpu_to_flash > flash, then you shouldn't have any direct connection between the CPU Data master and the flash. They should only be connected through the bridges.

The assign base address should really solve your problem, it just needs to move the ddr or the flash to prevent overlapping...

The descritor memory holds some parameters for the SGDMA, such as start address for a transfer, number of bytes, etc... They should be connected to the SGDMA descriptors read/write masters, and the CPU data master.

I think you need to declare the descriptors addresses somewhere in ipport.h too.

Hello There,

After following all the instruction/suggestion given by forum peoples my sopc wont be an error free it always says some connection error, some address overlapping error etc.

i am attaching the entire project please suggest/comment what went wrong in my sopc file,

i am trying to add on-chip memory (packet memory) to hold the UDP packet (512 packet of size 512 )coming from remote terminal at a very high speed.

i have add a On-Chip Memory (Packet memory duel port), and it's S1 port connected to SGDMA read and write, S2 port connected to CPU tightly coupled Data master (no other connection on these two port S1 and S2). connect the descriptive memory to descriptive read and write port of SGDMA. made the base address of pipeline and clock crossing bridge is to zero., i have also ensure that CPU Data master connected only pb_cpu_to_flash and flash and no other direct connection between CPU data master and flash

With regards

kaushal

Hello Daixiewn,

yes i ensure that my components are only connected behind the pipeline/clock crossing bridges. the way you says in your post, CUP Data master > pb_cpu_to_flash > flash, then there is no direct connection between the CPU Data master and the flash. They should only be connected through the bridges. i have reassign base address too but it won't able to solve problem.

Regards

kaushal

It seems that SOPC Builder isn't able to map the peripherals in your system when forcing the bridges to address 0 to prevent an address shift. It is strange, in my experience this always worked...

I tried a different strategy. I unlocked all the bridge addresses, and saw after the base address assignment that there are two block that use two addresses: ddr2_bot and descriptor_memory.

I collapse all the components (View menu) to have a better overview. Upon a first look I saw that you had some pipelines that weren't very useful. If you use a clock crossing bridge you don't really need to combine it with a pipeline bridge. So I removed pb_dma_to_ddr2, pb_cpu_to_io and pb_cpu_to_flash. Then I reran an assign base address.

Then I right click on ddr2_bot, go to connections > s1 and see that it is connected to pb_cpu_to_ddr2_bot and ccb_dma_to_ddr2. Since locking those two bridges to 0 didn't work I tried to do the contrary. I locked the pipeline bridge from the cpu to its current address (0x08000000) and modified and locked the address on the other pipeline bridge to match. Then I did the same thing with the descriptor memory. I locked the ccb_cpu_to_io address to 0x10000000 and modified and locked the pb_dma_to_descriptor_ram to the same address.

Hello Daixiwen,

Thanking you ,i follow the suggestion you given to me and finally my SOPC system won't give any error.

attached is the print screen of my SOPC maping

once again thanking you.:)

With Regards

kaushal

I have done the following steps to add the On-Chip memory to receive the incoming UDP packet.

1. Add an On Chip Memory (6553) through SOPC builder.

2. Generate the System

3. Compile the Nios-II Processor

4. Do the Desire Changes in IPPORT.H file (please see the attached ALTERA_PKT_MEM file this is the desire section of ipport.h file). This changes is as par readme file from the Ethernet_Accel_Design.Zip (Title: enabling the fast packet memory optimization)

5. After that I run the code on nios processor: and resultant nothing happen I mean TSE_MAC not initialize etc totally blank console. Otherwise it shows the initilize the tse_mac, outo_negtation, then simple_socket starting up, ip address is 192.168.1.205 etc

6. Is my SOPC connection of descriptor memory is properly connected or something missing…?

7. Do I add something in Nios BSP editor as this packet memory visible in BSP Editor?