mSG-DMA IRQ could not be cleared

Hi,

I encountered the case that the IRQ bit in mSG-DMA status could not be cleared.

I supplied descriptors for the MM-ST direction. The transfer size is small as 256Bytes. Every descriptor generates an interruption. Since the transfer size is small, interruptions may occur while the interruption service is executing.

The procedures after an interruption occurs are :

(1). Clear the interruption in the processor so that the next interruption can be

pended until the interruption service finished.

(2). Clear the IRQ in bit<9> of the mSG-DMA status.

(3). Do the interruption service program.

After clearing the IRQ bit, I read back the status.

In many cases,

the IRQ has been cleared

or

the IRQ is still set to 1 and the next interruption is pended by the processor(The processor'sinterruption status register indicates the interruption pending).

But in rare cases, although the IRQ is cleared, the IRQ is still 1 and no interruption is pended. As the result, Since I configured the interruption to MSI of PCIe, no interruption occurred after that and the IRQ keeps 1.

The PCIe legacy interruption system detects interruptions since it is a level interruption and the PCIe controller keeps interrupted until the IRQ in the mSG-DMA status is cleared.

I cleared the IRQ until it gets 0 and the interruptions occurs in the situation and I counted the number of IRQ-NOT-CLEARED. The ratio was 19 times in the 444405 interruptions(0.0043%).

I suspect that if the IRQ is cleared at the same time of the next interruption, IRQ does not go to 0 but keeps 1 and no MSI interruption TLP is sent.

The large size of the DMA never causes above since it (probably) interrupts out of the interruption service.

Does anyone experience the similar phenomenon or know any errata or application note describing about the IRQ clearance related above?

Thank you in advance.