Forum Discussion
Altera_Forum
Honored Contributor
9 years ago --- Quote Start --- Hi, I encountered the case that the IRQ bit in mSG-DMA status could not be cleared. --- Quote End --- First question: Are you only send as many "valids" and bytes as the DMA expects, or are you overrunning or underfilling the buffer? Second: Are you doing single transfers, or are you doing descriptor polling or park mode or anything else fancy?