mpeg ts interface ip core

Well this is my IP(haven't tested the code, so look for those bugs), it will serve as input to your ASI module

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
 
entity mpeg_generator is
port(
       reset      : in std_logic;
       clk         : in std_logic;
       enable    : in std_logic;
 
       data_vld : out std_logic;
       data      : out std_logic_vector(7 downto 0)
);
end entity;
 
architecture rtl of mpeg_generator is
 
signal byte_counter : integer range 0 to 255;
 
begin
 
process(reset, clk)
begin
if(reset = '1')then
   byte_counter <= 0;
   data_vld <= '0';
   data <= x"00";
elsif(rising_edge(clk))then
   if(enable = '1')then
      byte_counter <= byte_counter + 1;
      data_vld <= '1';
 
      case byte_counter is
         when 0 => data <= x"47";
         when 1 => data <= x"1F";
         when 2 => data <= x"FF";
         when 3 => data <= x"10";
         when 4 to 187 => data <= std_logic_vector(to_unsigned(byte_counter,8));
         when others => data_vld <= '0'; data <= x"00";
      end case;
   end if;
end if;
end process;
 
end rtl;

thanks for your reply, but i have a question:did ALTERA have any solution for an mpeg encoder generating those signals for the ASI-TX? if yes where i can find the ip? (specially the file .bsf ) and finally which signals we should input in this encoder?

I am sorry I don't know what altera has on offer, you can check their site for IP cores. The term mpeg_encoder refers to something more involved, it is encoding video data by compression techniques - too involved in fact.

thank you again for your attention about my subject. in your description of your bloc generating the 8 bit and the data valid, you don't mentioned an mpeg ts signals in the input? i though that we should have a mpeg ts packet in the input (188 or 204 bytes like it mentioned in the standard EN 50083-9)????????????

The above code generates 188 bytes packet. The sync word and other header bytes are defined. The rest of bytes are given just count values for you to check in the final testing of your ASI converter(i.e. if you recover your ASI back you should be able to see if it is working correctly).

sorry if i persist, but what do you means by "The above code generates 188 bytes packet"? your code generate a parallel 8bit data and a data_valid bit is it?

Basically we need 8 bit data. then a sequence of 188 such bytes is called an mpeg packet. A sequence of 204 bytes is also legal. you can do that by altering my code slightly to make data_valid high for further 16 bytes.

thanks kaz for your attention..

@zabarotta