The above code generates 188 bytes packet. The sync word and other header bytes are defined. The rest of bytes are given just count values for you to check in the final testing of your ASI converter(i.e. if you recover your ASI back you should be able to see if it is working correctly).
The enable is there if you need it otherwise set it to '1';
the data represents ts packets.
The above code generates two outputs, data and data_valid and these together with clk are to be connected to your ASI block, then you need another 270MHz clock for your ASI block.
You can generate symbol(BSF) if you compile the code in quartus. Alternatively you can interface by code to your ASI bsf, up to you.