mpeg ts interface ip core

Well this is my IP(haven't tested the code, so look for those bugs), it will serve as input to your ASI module

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
 
entity mpeg_generator is
port(
       reset      : in std_logic;
       clk         : in std_logic;
       enable    : in std_logic;
 
       data_vld : out std_logic;
       data      : out std_logic_vector(7 downto 0)
);
end entity;
 
architecture rtl of mpeg_generator is
 
signal byte_counter : integer range 0 to 255;
 
begin
 
process(reset, clk)
begin
if(reset = '1')then
   byte_counter <= 0;
   data_vld <= '0';
   data <= x"00";
elsif(rising_edge(clk))then
   if(enable = '1')then
      byte_counter <= byte_counter + 1;
      data_vld <= '1';
 
      case byte_counter is
         when 0 => data <= x"47";
         when 1 => data <= x"1F";
         when 2 => data <= x"FF";
         when 3 => data <= x"10";
         when 4 to 187 => data <= std_logic_vector(to_unsigned(byte_counter,8));
         when others => data_vld <= '0'; data <= x"00";
      end case;
   end if;
end if;
end process;
 
end rtl;