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Altera_Forum's avatar
Altera_Forum
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18 years ago

Modelsim functional simulation of DDR2 HP controller

Hello, I wanted to set up a functional simulation of DDR2 high performance controller to evaluate some design features. But the verilog part of the core uses defparam statements for generic par...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Hello,

I found, that the problem was due to Modelsim VHDL and Verilog libraries using the same directory below fpgalibs. With VHDL version compiled last, the simulation fails. You have to recompile the Verilog version of altera_mf and lpm first. This is not obvious, cause Modelsim generally can include VHDL modules and libraries (with mixed language option license) but can't use generics with defparam (why ever).

Instantiating Verilog modules with defparam always works. For this reason, Altera generally uses old style# parameter syntax in Verilog VHDL-wrapper modules.

Verilog experts probably would have known...

Regards,

Frank